Jared Zerbe

Publication Activity (10 Years)

Years Active: 1994-2015
Publications (10 Years): 0

Top Topics

Generalization Bounds

Top Venues

IEEE J. Solid State Circuits

Publications

Reza Navid, E.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. IEEE J. Solid State Circuits 50 (4) (2015)
Masum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface. IEEE J. Solid State Circuits 49 (4) (2014)
E.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
A 40-Gb/s serial link transceiver in 28-nm CMOS technology. VLSIC (2014)
Masum Hossain, E.-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-Huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering. VLSIC (2014)
Masum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching. CICC (2012)
Dustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. CICC (2012)
Kambiz Kaviani, Masum Hossain, Meisam Honarvar Nazari, Fred Heaton, Jihong Ren, Jared Zerbe
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS. CICC (2012)
Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. IEEE J. Solid State Circuits 46 (4) (2011)
Jaeha Kim, E.-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2011)
John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John M. Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen
Power-efficient I/O design considerations for high-bandwidth applications. CICC (2011)
Jaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe
Equalizer design and performance trade-offs in ADC-based serial links. CICC (2010)
Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. IEEE J. Solid State Circuits 44 (4) (2009)
E.-Hung Chen, Jihong Ren, Brian S. Leibowitz, Haechang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic, Jared Zerbe, Chih-Kong Ken Yang
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric. IEEE J. Solid State Circuits 43 (9) (2008)
Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. ISSCC (2007)
Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz
Improving CDR Performance via Estimation. ISSCC (2006)
Carl W. Werner, C. Hoyer, Andrew Ho, Metha Jeeradit, Fred Chen, Bruno W. Garlepp, Bill Stonecypher, Simon Li, Akash Bansal, Amita Agarwal, Elad Alon, Vladimir Stojanovic, Jared Zerbe
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system. CICC (2005)
Anthony G. Bessios, William F. Stonecypher, Amita Agarwal, Jared Zerbe
Transition-limiting codes for 4-PAM signaling in high speed serial links. GLOBECOM (2003)
Matthew M. Griffin, Jared Zerbe, Grace Tsang, Michael Ching, Clemenz L. Portmann
A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation. IEEE J. Solid State Circuits 33 (11) (1998)
Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM. IEEE J. Solid State Circuits 29 (12) (1994)