Patrick Satarzadeh

Publication Activity (10 Years)

Years Active: 2007-2019
Publications (10 Years): 1

Top Topics

Evolutionary Algorithm

Delta Sigma Modulators

Top Venues

Publications

Garen Hovakimyan, Pirooz Hojabri, Gregory A. Martin, Patrick Satarzadeh
Digital Correction of Time Interleaved DAC Mismatches. ISCAS (2019)
Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi
-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. ISSCC (2012)
Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. IEEE J. Solid State Circuits 46 (4) (2011)
Jaeha Kim, E.-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2011)
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs. ISCAS (2010)
Jaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe
Equalizer design and performance trade-offs in ADC-based serial links. CICC (2010)
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
Digital Calibration of a Nonlinear S/H. IEEE J. Sel. Top. Signal Process. 3 (3) (2009)
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter. ISCAS (2007)