Chih-Kong Ken Yang

Publication Activity (10 Years)

Years Active: 1996-2022
Publications (10 Years): 12

Top Topics

Cmos Technology

Nonlinear Regression

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Jiazhang Song, Li-Yang Chen, Mau-Chung Frank Chang, Sudhakar Pamarti, Chih-Kong Ken Yang
A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input. ISCAS (2022)
Li-Yang Chen, Abhinav Kumar Vinod, James F. McMillan, Hangbo Yang, Chee Wei Wong, Chih-Kong Ken Yang
A Pulsed-Coherent Lidar With Sub-10 μm Precision. IEEE J. Solid State Circuits 57 (8) (2022)
Mostafa Toubar, Yousr Ismail, Sameh Ibrahim, Chih-Kong Ken Yang
A Scalable 20V Charge-Pump-Based Driver in 65nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 69 (1) (2022)
Li-Yang Chen, Abhinav Kumar Vinod, James McMillan, Chee Wei Wong, Chih-Kong Ken Yang
A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGA. CICC (2021)
Liangxiao Tang, Weixin Gai, Chih-Kong Ken Yang, Bingyi Ye, Congcong Chen
A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. ISCAS (2021)
Yan Zhang, Chia-Jen Liang, Christopher Chen, Andrew Liu, Jason Woo, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang
A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS. ESSCIRC (2021)
Mahmoud R. Elhebeary, Chih-Kong Ken Yang
A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot. IEEE Trans. Circuits Syst. (12) (2020)
Mahmoud R. Elhebeary, Chih-Kong Ken Yang
A 92%-Efficiency Battery Powered Hybrid DC-DC Converter for IoT Applications. IEEE Trans. Circuits Syst. (10) (2020)
Mahmoud R. Elhebeary, Chih-Kong Ken Yang
An 85%-Efficiency Hybrid DC-DC Converter for Sub-Microwatt IoT Applications. MWSCAS (2019)
Mahmoud R. Elhebeary, Li-Yang Chen, Sudhakar Pamarti, Chih-Kong Ken Yang
An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications. ESSCIRC (2019)
Li-Yang Chen, Chih-Kong Ken Yang
A 19-GHz Pulsed-Coherent ToF Receiver With 40-μm Precision for Laser Ranging Systems. ESSCIRC (2019)
Yousr Ismail, Haechang Lee, Sudhakar Pamarti, Chih-Kong Ken Yang
A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology. IEEE J. Solid State Circuits 52 (3) (2017)
Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang
A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50 (3) (2015)
Won Ho Park, Chih-Kong Ken Yang
Effects of Active Cooling on Workload Management in High Performance Processors. CLOSER (2015)
Ming-Shuan Chen, Chih-Kong Ken Yang
A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50 (8) (2015)
Ming-Shuan Chen, Mau-Chung Frank Chang, Chih-Kong Ken Yang
A low-PDP and low-area repeater using passive CTLE for on-chip interconnects. VLSIC (2015)
Jintae Kim, Siamak Modjtahedi, Chih-Kong Ken Yang
A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Henry Park, Chih-Kong Ken Yang
Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Yousr Ismail, Chih-Kong Ken Yang
A 12-V charge pump-based square wave driver in 65-nm CMOS technology. A-SSCC (2014)
Jintae Kim, Siamak Modjtahedi, Chih-Kong Ken Yang
Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters. IEEE Trans. Very Large Scale Integr. Syst. 22 (9) (2014)
Ming-Shuan Chen, Chih-Kong Ken Yang
A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS. CICC (2014)
Yousr Ismail, Chih-Kong Ken Yang
A compact stacked-device output driver in low-voltage CMOS Technology. ISCAS (2014)
Yousr Ismail, Haechang Lee, Sudhakar Pamarti, Chih-Kong Ken Yang
23.8 A 34V charge pump in 65nm bulk CMOS technology. ISSCC (2014)
Henry Park, Chih-Kong Ken Yang
In Situ SRAM Static Stability Estimation in 65-nm CMOS. IEEE J. Solid State Circuits 48 (10) (2013)
Won Ho Park, Chih-Kong Ken Yang
Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors. IEEE Trans. Very Large Scale Integr. Syst. 21 (9) (2013)
Ramy Yousry, Henry Park, E.-Hung Chen, Chih-Kong Ken Yang
A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS. ISCAS (2013)
Tamer A. Ali, Robert J. Drost, Ron Ho, Chih-Kong Ken Yang
A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding. IEEE J. Solid State Circuits 48 (4) (2013)
Ming-Shuan Chen, Amr Amin Hafez, Chih-Kong Ken Yang
A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection. IEEE J. Solid State Circuits 48 (11) (2013)
Henry Park, Chih-Kong Ken Yang
An INL Yield Model of the Digital-to-Analog Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Amr Amin Hafez, Chih-Kong Ken Yang
Analysis and Design of Superharmonic Injection-Locked Multipath Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2013)
Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang
A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS. ISSCC (2013)
Fengbo Ren, Henry Park, Chih-Kong Ken Yang, Dejan Markovic
Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2013)
Yousr Ismail, Chang-Jin Kim, Chih-Kong Ken Yang
A bipolar >40-V driver in 45-nm SOI CMOS technology. CICC (2013)
Tamer A. Ali, Won Ho Park, Preeti Mulage, E.-Hung Chen, Ron Ho, Chih-Kong Ken Yang
A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding. VLSIC (2012)
Henry Park, Chih-Kong Ken Yang
Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter. IEEE Trans. Circuits Syst. II Express Briefs (9) (2012)
Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic
A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). ISQED (2012)
Ming-Shuan Chen, Chih-Kong Ken Yang
A low-power highly multiplexed parallel PRBS generator. CICC (2012)
E.-Hung Chen, Ramy Yousry, Chih-Kong Ken Yang
Power Optimized ADC-Based Serial Link Receiver. IEEE J. Solid State Circuits 47 (4) (2012)
Tamer A. Ali, Amr Amin Hafez, Robert J. Drost, Ronald Ho, Chih-Kong Ken Yang
A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning. ISSCC (2011)
Henry Park, Richard Dorrance, Amr Amin Hafez, Fengbo Ren, Dejan Markovic, Chih-Kong Ken Yang
Analysis of STT-RAM cell design with multiple MTJs per access. NANOARCH (2011)
Amr Amin Hafez, Chih-Kong Ken Yang
Design and Optimization of Multipath Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2011)
Jaeha Kim, E.-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2011)
Jintae Kim, S. Limotyrakis, Chih-Kong Ken Yang
Multilevel Power Optimization of Pipelined A/D Converters. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Richard Dorrance, Fengbo Ren, Yuta Toriyama, Amr Amin Hafez, Chih-Kong Ken Yang, Dejan Markovic
Scalability and design-space analysis of a 1T-1MTJ memory cell. NANOARCH (2011)
E.-Hung Chen, Chih-Kong Ken Yang
ADC-Based Serial I/O Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2010)
Tamer A. Ali, Dinesh Patil, Frankie Liu, Elad Alon, Jon K. Lexau, Chih-Kong Ken Yang, Ron Ho
Clocking Links in Multi-chip Packages: A Case Study. Hot Interconnects (2010)
Vladimir Stojanovic, Chih-Kong Ken Yang, Ron Ho
Guest Editorial for Special Issue on High-Performance Multichip Interconnections. IEEE Trans. Circuits Syst. II Express Briefs (5) (2010)
Jintae Kim, Lieven Vandenberghe, Chih-Kong Ken Yang
Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology. IEEE J. Solid State Circuits 45 (4) (2010)
Aida Varzaghani, Chih-Kong Ken Yang
A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization. IEEE J. Solid State Circuits 44 (3) (2009)
Chih-Kong Ken Yang, E.-Hung Chen
ADC-based serial I/O receivers. CICC (2009)
Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
A nonlinear phase detector for digital phase locked loops. CICC (2009)
Li-min Lee, Chih-Kong Ken Yang
An LC-Based Clock Buffer With Tunable Injection Locking. IEEE J. Solid State Circuits 44 (3) (2009)
James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi
A stochastic jitter model for analyzing digital timing-recovery circuits. DAC (2009)
Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages. IEEE J. Solid State Circuits 44 (9) (2009)
E.-Hung Chen, Jihong Ren, Brian S. Leibowitz, Haechang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic, Jared Zerbe, Chih-Kong Ken Yang
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric. IEEE J. Solid State Circuits 43 (9) (2008)
Utku Seckin, Chih-Kong Ken Yang
A Comprehensive Delay Model for CMOS CML Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2008)
Jackie Koon Lun Wong, E.-Hung Chen, Chih-Kong Ken Yang
Edge and Data Adaptive Equalization of Serial-Link Transceivers. IEEE J. Solid State Circuits 43 (9) (2008)
Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang
Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage. CICC (2008)
Azita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. IEEE J. Solid State Circuits 42 (4) (2007)
Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang
Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies. IEEE Trans. Very Large Scale Integr. Syst. 15 (9) (2007)
Jackie Koon Lun Wong, Alexander V. Rylyakov, Chih-Kong Ken Yang
A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions. IEEE J. Solid State Circuits 42 (4) (2007)
Ping-Hsuan Hsieh, Chih-Kong Ken Yang
Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs (3) (2007)
James R. Burnham, Gu-Yeon Wei, Chih-Kong Ken Yang, Haitham A. Hindi
A Comprehensive Phase-Transfer Model for Delay-Locked Loops. CICC (2007)
Jintae Kim, Hamid Hatamkhani, Chih-Kong Ken Yang
Swing. IEEE J. Solid State Circuits 42 (5) (2007)
Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang
Device-circuit co-optimization for mixed-mode circuit design via geometric programming. ICCAD (2007)
Li-min Lee, Chih-Kong Ken Yang
An Adaptive Low-Jitter LC-Based Clock Distribution. ISSCC (2007)
Koon-Lun Jackie Wong, Chih-Kong Ken Yang
A Serial-Link Transceiver with Transition Equalization. ISSCC (2006)
Hamid Hatamkhani, Chih-Kong Ken Yang
A Study of the Optimal Data Rate for Minimum Power of I/Os. IEEE Trans. Circuits Syst. II Express Briefs (11) (2006)
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang
Power-centric design of high-speed I/Os. DAC (2006)
Li-min Lee, Daniel Weinlader, Chih-Kong Ken Yang
A sub-10-ps multiphase sampling system using redundancy. IEEE J. Solid State Circuits 41 (1) (2006)
Aida Varzaghani, Chih-Kong Ken Yang
A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter. IEEE J. Solid State Circuits 41 (4) (2006)
Jintae Kim, Hamid Hatamkhani, Chih-Kong Ken Yang
swing. ISSCC (2006)
Aida Varzaghani, Chih-Kong Ken Yang
A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration. IEEE J. Solid State Circuits 41 (2) (2006)
Koon-Lun Jackie Wong, Chih-Kong Ken Yang
Offset compensation in comparators with minimum input-referred supply noise. IEEE J. Solid State Circuits 39 (5) (2004)
Jackie Koon Lun Wong, Hamid Hatamkhani, Mozhgan Mansuri, Chih-Kong Ken Yang
A 27-mW 3.6-gb/s I/O transceiver. IEEE J. Solid State Circuits 39 (4) (2004)
Jaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang
Evaluation of fully-integrated switching regulators for CMOS process technologies. SoC (2003)
Chih-Kong Ken Yang, Koon-Lun Jackie Wong
Analysis of timing recovery for multi-Gbps PAM transceivers. CICC (2003)
M. Mansuri, A. Hadiashar, Chih-Kong Ken Yang
Methodology for on-chip adaptive jitter minimization in phase-locked loops. IEEE Trans. Circuits Syst. II Express Briefs 50 (11) (2003)
Ping-Hsuan Hsieh, Jack Judy, Chih-Kong Ken Yang
CMOS LC oscillator using variable mean frequency. CICC (2003)
Mozhgan Mansuri, Chih-Kong Ken Yang
A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation. IEEE J. Solid State Circuits 38 (11) (2003)
Mozhgan Mansuri, Dean Liu, Chih-Kong Ken Yang
Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops. IEEE J. Solid State Circuits 37 (10) (2002)
Mozhgan Mansuri, Chih-Kong Ken Yang
Jitter optimization based on phase-locked loop design parameters. IEEE J. Solid State Circuits 37 (11) (2002)
Chih-Kong Ken Yang, Vladimir Stojanovic, Siamak Modjtahedi, Mark A. Horowitz, William F. Ellersick
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS. IEEE J. Solid State Circuits 36 (11) (2001)
Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. IEEE J. Solid State Circuits 35 (5) (2000)
Katayoun Falakshahi, Chih-Kong Ken Yang, Bruce A. Wooley
A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation. IEEE J. Solid State Circuits 34 (5) (1999)
Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. IEEE J. Solid State Circuits 34 (5) (1999)
Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos
High-speed electrical signaling: overview and limitations. IEEE Micro 18 (1) (1998)
Chih-Kong Ken Yang, Ramin Farjad-Rad, Mark A. Horowitz
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling. IEEE J. Solid State Circuits 33 (5) (1998)
Chih-Kong Ken Yang, Mark A. Horowitz
A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links. IEEE J. Solid State Circuits 31 (12) (1996)