Stefanos Sidiropoulos

Publication Activity (10 Years)

Years Active: 1991-2022
Publications (10 Years): 1

Top Topics

Recognition Scheme

Analog To Digital Converter

Top Venues

VLSI Technology and Circuits

IEEE J. Solid State Circuits

Publications

Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos
A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. VLSI Technology and Circuits (2022)
Aida Varzaghani, Athos Kasapi, Dimitri Loizos, Song-Hee Paik, Shwetabh Verma, Sotirios Zogopoulos, Stefanos Sidiropoulos
A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications. IEEE J. Solid State Circuits 48 (12) (2013)
Shwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos, Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropoulos
A 10.3GS/s 6b flash ADC for 10G Ethernet applications. ISSCC (2013)
Shahriar Rabii, Nikhil Acharya, Pak Chau, Joseph Dao, Arnold Feldman, Haw-Jyh Liaw, Dean Liu, Marc Loinaz, Manuel Luschas, Azmeer Salleh, Siddharth Sheth, Stefanos Sidiropoulos, Donald Stark, Shwetabh Verma
An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS. ISSCC (2006)
Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz
Improving CDR Performance via Estimation. ISSCC (2006)
Dean Liu, Stefanos Sidiropoulos, Mark Horowitz
A Framework for Designing Reusable Analog Circuits. ICCAD (2003)
Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. IEEE J. Solid State Circuits 38 (5) (2003)
Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, Mark A. Horowitz
A variable-frequency parallel I/O interface with adaptive power-supply regulation. IEEE J. Solid State Circuits 35 (11) (2000)
Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos
High-speed electrical signaling: overview and limitations. IEEE Micro 18 (1) (1998)
Stefanos Sidiropoulos, Mark A. Horowitz
A semidigital dual delay-locked loop. IEEE J. Solid State Circuits 32 (11) (1997)
Stefanos Sidiropoulos, Mark Horowitz
A 700-Mb/s/pin CMOS signaling interface using current integrating receivers. IEEE J. Solid State Circuits 32 (5) (1997)
Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon
A speed, power, and supply noise evaluation of ECL driver circuits. IEEE J. Solid State Circuits 31 (1) (1996)
Manolis Katevenis, Stefanos Sidiropoulos, Costas Courcoubetis
Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip. IEEE J. Sel. Areas Commun. 9 (8) (1991)