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A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.
Kun-Yung Ken Chang
Jason Wei
Charlie Huang
Simon Li
Kevin S. Donnelly
Mark Horowitz
Yingxuan Li
Stefanos Sidiropoulos
Published in:
IEEE J. Solid State Circuits (2003)
Keyphrases
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high speed
ultra low power
low power
analog vlsi
low cost
cmos image sensor
circuit design
single chip
phase locked loop
power consumption
cmos technology
focal plane
chip design
image sensor
power dissipation
mixed signal
nm technology
random access memory
metal oxide semiconductor
silicon on insulator