Kevin S. Donnelly

Publication Activity (10 Years)

Years Active: 1994-2003
Publications (10 Years): 0

Publications

Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic, Fred Chen, Jason Wei, Grace Tsang, Dennis Kim, William F. Stonecypher, Andrew Ho, Timothy P. Thrush, Ravi T. Kollipara, Mark A. Horowitz, Kevin S. Donnelly
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. IEEE J. Solid State Circuits 38 (12) (2003)
Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. IEEE J. Solid State Circuits 38 (5) (2003)
Jared L. Zerbe, Pak Shing Chau, Carl W. Werner, Timothy P. Thrush, H. J. Liaw, Bruno W. Garlepp, Kevin S. Donnelly
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus. IEEE J. Solid State Circuits 36 (5) (2001)
Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz
A portable digital DLL for high-speed CMOS interface circuits. IEEE J. Solid State Circuits 34 (5) (1999)
Benedict Lau, Yiu-Fai Chan, Alfredo Moncayo, John Ho, Mike Allen, Joe Salmon, Jonathan Liu, Manish Muthal, Cliff Lee, Tim Nguyen, Bryce Horine, Mike Leddige, Kuojim Huang, Jason Wei, Leung Yu, Richard Tarver, Yuwen Hsia, Roxanne Vu, Ely Tsern, Haw-Jyh Liaw, Jim Hudson, David Nguyen, Kevin S. Donnelly, Richard Crisp
A 2.6-GByte/s multipurpose chip-to-chip interface. IEEE J. Solid State Circuits 33 (11) (1998)
Kevin S. Donnelly, Yiu-Fai Chan, John Ho, Chanh Tran, Samir Patel, Benedict Lau, Jun Kim, Pak Shing Chau, Charlie Huang, Jason Wei, Leung Yu, Richard Tarver, Rakhee Kulkarni, Donald Stark, Mark Johnson
A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC. IEEE J. Solid State Circuits 31 (12) (1996)
Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM. IEEE J. Solid State Circuits 29 (12) (1994)