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A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM.
Thomas H. Lee
Kevin S. Donnelly
John T. C. Ho
Jared Zerbe
Mark Johnson
Tom Ishikawa
Published in:
IEEE J. Solid State Circuits (1994)
Keyphrases
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low voltage
power dissipation
cmos technology
high speed
power consumption
low cost
main memory
high density
analog vlsi
random access memory
design considerations
circuit design
neural network
feedback loop
low power
image sensor
critical path
power management
single chip
wireless sensor networks
image processing