Carl W. Werner

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 1

Top Topics

Protein Folding

Electron Microscopy

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Richelle L. Smith, Masum Hossain, Carl W. Werner, Joseph M. Kahn, Thomas H. Lee
Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (8) (2023)
Shreyas Sen, Farshid Aryanfar, Carl W. Werner
A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels. IEEE Trans. Circuits Syst. II Express Briefs (9) (2011)
Ting Wu, Farshid Aryanfar, Haechang Lee, Jie Shen, T. J. Chin, Carl W. Werner, Ken Chang
Low-skew clock distribution using zero-phase-clock-buffer DLLs. ISSCC (2010)
Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. ISSCC (2007)
Carl W. Werner, C. Hoyer, Andrew Ho, Metha Jeeradit, Fred Chen, Bruno W. Garlepp, Bill Stonecypher, Simon Li, Akash Bansal, Amita Agarwal, Elad Alon, Vladimir Stojanovic, Jared Zerbe
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system. CICC (2005)
Vladimir Stojanovic, Andrew Ho, Bruno W. Garlepp, Fred Chen, Jason Wei, Grace Tsang, Elad Alon, Ravi T. Kollipara, Carl W. Werner, Jared L. Zerbe, Mark A. Horowitz
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. IEEE J. Solid State Circuits 40 (4) (2005)
Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic, Fred Chen, Jason Wei, Grace Tsang, Dennis Kim, William F. Stonecypher, Andrew Ho, Timothy P. Thrush, Ravi T. Kollipara, Mark A. Horowitz, Kevin S. Donnelly
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. IEEE J. Solid State Circuits 38 (12) (2003)
Jared L. Zerbe, Pak Shing Chau, Carl W. Werner, Timothy P. Thrush, H. J. Liaw, Bruno W. Garlepp, Kevin S. Donnelly
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus. IEEE J. Solid State Circuits 36 (5) (2001)