Ramin Farjad-Rad

Publication Activity (10 Years)

Years Active: 1998-2020
Publications (10 Years): 2

Top Topics

Graphical User Interface

Error Correction

Communication Protocol

Top Venues

Hot Interconnects

Hot Chips Symposium

Publications

Shahab Ardalan, Halil Cirit, Ramin Farjad-Rad, Mark Kuemerle, Ken Poulton, Suresh Subramanian, Bapiraju Vinnakota
Bunch of Wires: An Open Die-to-Die Interface. Hot Interconnects (2020)
Ramin Shirani, Ramin Farjad-Rad
10G | 5G | 2.5G | 1G | 100M physical layer PHY: HOT CHIPS 2015 conference. Hot Chips Symposium (2015)
Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng
A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. IEEE J. Solid State Circuits 47 (12) (2012)
Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani
A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. ISSCC (2012)
Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. ISSCC (2007)
Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. IEEE J. Solid State Circuits 39 (9) (2004)
Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan
Jitter transfer characteristics of delay-locked loops - theories and design techniques. IEEE J. Solid State Circuits 38 (4) (2003)
Hiok-Tiaq Ng, M.-J. Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. CICC (2003)
M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton
CMOS High-Speed I/Os - Present and Future. ICCD (2003)
Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan
A second-order semidigital clock recovery circuit based on injection locking. IEEE J. Solid State Circuits 38 (12) (2003)
Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid State Circuits 37 (12) (2002)
Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. IEEE J. Solid State Circuits 35 (5) (2000)
Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. IEEE J. Solid State Circuits 34 (5) (1999)
Chih-Kong Ken Yang, Ramin Farjad-Rad, Mark A. Horowitz
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling. IEEE J. Solid State Circuits 33 (5) (1998)