Bruno W. Garlepp

Publication Activity (10 Years)

Years Active: 1999-2010
Publications (10 Years): 0

Publications

Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp
A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator. IEEE J. Solid State Circuits 45 (12) (2010)
Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp
A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator. ISSCC (2010)
Jafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications. IEEE J. Solid State Circuits 43 (5) (2008)
Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. IEEE J. Solid State Circuits 43 (4) (2008)
Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz
A new technique for characterization of digital-to-analog converters in high-speed systems. DATE (2007)
Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. ISSCC (2007)
Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore
A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. IEEE J. Solid State Circuits 41 (12) (2006)
Derrick C. Wei, Yunteng Huang, Bruno W. Garlepp, Jerrell P. Hein
A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation. ISSCC (2006)
Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Ligang Zhang, Jerrell P. Hein
A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. ISSCC (2006)
Carl W. Werner, C. Hoyer, Andrew Ho, Metha Jeeradit, Fred Chen, Bruno W. Garlepp, Bill Stonecypher, Simon Li, Akash Bansal, Amita Agarwal, Elad Alon, Vladimir Stojanovic, Jared Zerbe
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system. CICC (2005)
Vladimir Stojanovic, Andrew Ho, Bruno W. Garlepp, Fred Chen, Jason Wei, Grace Tsang, Elad Alon, Ravi T. Kollipara, Carl W. Werner, Jared L. Zerbe, Mark A. Horowitz
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. IEEE J. Solid State Circuits 40 (4) (2005)
Jared L. Zerbe, Pak Shing Chau, Carl W. Werner, Timothy P. Thrush, H. J. Liaw, Bruno W. Garlepp, Kevin S. Donnelly
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus. IEEE J. Solid State Circuits 36 (5) (2001)
Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz
A portable digital DLL for high-speed CMOS interface circuits. IEEE J. Solid State Circuits 34 (5) (1999)