A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition.
Michael H. PerrottYunteng HuangRex T. BairdBruno W. GarleppDouglas PastorelloEric T. KingQicheng YuDan B. KashaPhilip SteinerLigang ZhangJerrell P. HeinBruce Del SignorePublished in: IEEE J. Solid State Circuits (2006)