Jerrell P. Hein

Publication Activity (10 Years)

Years Active: 1998-2006
Publications (10 Years): 0

Publications

Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore
A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. IEEE J. Solid State Circuits 41 (12) (2006)
Derrick C. Wei, Yunteng Huang, Bruno W. Garlepp, Jerrell P. Hein
A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation. ISSCC (2006)
Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Ligang Zhang, Jerrell P. Hein
A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. ISSCC (2006)
G. Diwakar Vishakhadatta, Russell Croman, Marius Goldenberg, Jerrell P. Hein, Pradeep Katikaneni, Diana Kuai, Cathy Lee, Ion Constatin Tesu, Richard Trujillo, Ligang Zhang, Kent Anderson, Richard Behrens, William Bliss, Li Du, Trent Dudley, German Feyh, William Foland, Michael Kastner, Qingfen Li, Jeff Mitchem, David Reed, Sian She, Mark Spurbeck, Lisa Sundell, Hoai Tran, Maoxin Wei, Christopher Zook
An EPR4 read/write channel with digital timing recovery. IEEE J. Solid State Circuits 33 (11) (1998)