Michael H. Perrott

Publication Activity (10 Years)

Years Active: 1997-2014
Publications (10 Years): 0

Top Venues

ISSCC

IEEE J. Solid State Circuits

ISCAS

Massachusetts Institute of Technology, Cambridge, MA, USA (PHD)

Education History

Massachusetts Institute of Technology, Cambridge, MA, USA

PHD

Publications

Mohammad Alhawari, Nadya Albelooshi, Michael H. Perrott
A 0.5 V < 4 µW CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor. IEEE J. Solid State Circuits 49 (1) (2014)
Mohammad Alhawari, Michael H. Perrott
A clockless, multi-stable, CMOS analog circuit. ISCAS (2014)
Mohammad Alhawari, Nadya Albelooshi, Michael H. Perrott
A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer. ISSCC (2013)
Michael H. Perrott, Geert Van der Plas
Session 15 overview: Data converter techniques. ISSCC (2013)
Michael H. Perrott, James C. Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi
A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter. IEEE J. Solid State Circuits 48 (1) (2013)
Michael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi
A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability. ISSCC (2012)
Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski
An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2011)
Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp
A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator. IEEE J. Solid State Circuits 45 (12) (2010)
Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski
A Time-Domain Resolution Improvement of an RF-DAC. IEEE Trans. Circuits Syst. II Express Briefs (7) (2010)
Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp
A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator. ISSCC (2010)
Belal Helal, Chun-Ming Hsu, Kerwin Johnson, Michael H. Perrott
A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop. IEEE J. Solid State Circuits 44 (5) (2009)
Min C. Park, Michael H. Perrott
A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer. ISSCC (2009)
Min C. Park, Michael H. Perrott
A Single-slope 80MS/s ADC using Two-Step Time-to-Digital Conversion. ISCAS (2009)
Matthew Park, Michael H. Perrott
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 µm CMOS. IEEE J. Solid State Circuits 44 (12) (2009)
Matthew Z. Straayer, Michael H. Perrott
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping. IEEE J. Solid State Circuits 44 (4) (2009)
Min C. Park, Michael H. Perrott
A VCO-based Analog-to-digital Converter with Second-order Sigma-Delta Noise Shaping. ISCAS (2009)
Matthew Z. Straayer, Michael H. Perrott
A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer. IEEE J. Solid State Circuits 43 (4) (2008)
Belal Helal, Matthew Z. Straayer, Gu-Yeon Wei, Michael H. Perrott
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance. IEEE J. Solid State Circuits 43 (4) (2008)
Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott
A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. ISSCC (2008)
Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott
A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. IEEE J. Solid State Circuits 43 (12) (2008)
Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore
A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. IEEE J. Solid State Circuits 41 (12) (2006)
Scott E. Meninger, Michael H. Perrott
A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise. IEEE J. Solid State Circuits 41 (4) (2006)
Ethan Crain, Michael H. Perrott
A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation. IEEE J. Solid State Circuits 41 (2) (2006)
Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Ligang Zhang, Jerrell P. Hein
A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. ISSCC (2006)
Ethan Crain, Michael H. Perrott
A numerical design approach for high speed, differential, resistor-loaded, CMOS amplifiers. ISCAS (5) (2004)
Michael H. Perrott, Gu-Yeon Wei
Guest editorial. IEEE Trans. Circuits Syst. II Express Briefs 50 (11) (2003)
Charlotte Y. Lau, Michael H. Perrott
Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm. DAC (2003)
Scott E. Meninger, Michael H. Perrott
A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise. IEEE Trans. Circuits Syst. II Express Briefs 50 (11) (2003)
Michael H. Perrott
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits. DAC (2002)
Michael H. Perrott
Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits. IEEE Des. Test Comput. 19 (4) (2002)
Michael H. Perrott, Mitchell D. Trott, Charles G. Sodini
A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis. IEEE J. Solid State Circuits 37 (8) (2002)
Michael H. Perrott, Theodore L. Tewksbury III, Charles G. Sodini
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation. IEEE J. Solid State Circuits 32 (11) (1997)

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Publication Activity (10 Years)

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Michael H. Perrott