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A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise.
Scott E. Meninger
Michael H. Perrott
Published in:
IEEE J. Solid State Circuits (2006)
Keyphrases
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high speed
low power
power consumption
real time
cmos technology