A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation.

Ethan Crain Michael H. Perrott

Published in: IEEE J. Solid State Circuits (2006)

Keyphrases

high speed
low power
high power
low cost
analog vlsi
power consumption
power supply
image processing
circuit design
single chip
database
data sets
databases
delay insensitive