Yunteng Huang

Publication Activity (10 Years)

Years Active: 1998-2006
Publications (10 Years): 0

Publications

Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore
A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. IEEE J. Solid State Circuits 41 (12) (2006)
Derrick C. Wei, Yunteng Huang, Bruno W. Garlepp, Jerrell P. Hein
A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation. ISSCC (2006)
Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Ligang Zhang, Jerrell P. Hein
A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. ISSCC (2006)
Hirokazu Yoshizawa, Yunteng Huang, Paul F. Ferguson Jr., Gabor C. Temes
MOSFET-only switched-capacitor circuits in digital CMOS technology. IEEE J. Solid State Circuits 34 (6) (1999)
Yunteng Huang, Gabor C. Temes, Paul F. Ferguson Jr.
Offset- and gain-compensated track-and-hold stages. ICECS (1998)