Ravi T. Kollipara

Publication Activity (10 Years)

Years Active: 2003-2014
Publications (10 Years): 0

Top Topics

Building Blocks

Human Machine Interface

Top Venues

IEEE J. Solid State Circuits

Publications

Michael Bucher, Ravi T. Kollipara, Bruce Su, Liji Gopalakrishnan, Kashinath Prabhu, Pravin Kumar Venkatesan, Kambiz Kaviani, Barry Daly, William F. Stonecypher, Wayne D. Dettloff, Teva Stone, Fred Heaton, Yi Lu, Chris J. Madden, Sanath Bangalore, John C. Eble, Nhat Nguyen, Lei Luo
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems. IEEE J. Solid State Circuits 49 (1) (2014)
Kambiz Kaviani, Michael Bucher, Bruce Su, Barry Daly, Bill Stonecypher, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Pravin Kumar Venkatesan, Fred Heaton, Ravi T. Kollipara, Yi Lu, Chris J. Madden, John C. Eble, Lei Luo, Nhat Nguyen
A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems. ISSCC (2013)
Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. IEEE J. Solid State Circuits 46 (4) (2011)
Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. IEEE J. Solid State Circuits 43 (4) (2008)
Vladimir Stojanovic, Andrew Ho, Bruno W. Garlepp, Fred Chen, Jason Wei, Grace Tsang, Elad Alon, Ravi T. Kollipara, Carl W. Werner, Jared L. Zerbe, Mark A. Horowitz
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. IEEE J. Solid State Circuits 40 (4) (2005)
Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic, Fred Chen, Jason Wei, Grace Tsang, Dennis Kim, William F. Stonecypher, Andrew Ho, Timothy P. Thrush, Ravi T. Kollipara, Mark A. Horowitz, Kevin S. Donnelly
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. IEEE J. Solid State Circuits 38 (12) (2003)