Login / Signup
Kashinath Prabhu
Publication Activity (10 Years)
Years Active: 2009-2014
Publications (10 Years): 0
Top Topics
Memory Usage
Human Machine Interface
Vlsi Architecture
Low Power
Top Venues
CICC
ISSCC
IEEE J. Solid State Circuits
</>
Publications
</>
Michael Bucher
,
Ravi T. Kollipara
,
Bruce Su
,
Liji Gopalakrishnan
,
Kashinath Prabhu
,
Pravin Kumar Venkatesan
,
Kambiz Kaviani
,
Barry Daly
,
William F. Stonecypher
,
Wayne D. Dettloff
,
Teva Stone
,
Fred Heaton
,
Yi Lu
,
Chris J. Madden
,
Sanath Bangalore
,
John C. Eble
,
Nhat Nguyen
,
Lei Luo
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems.
IEEE J. Solid State Circuits
49 (1) (2014)
Kambiz Kaviani
,
Michael Bucher
,
Bruce Su
,
Barry Daly
,
Bill Stonecypher
,
Wayne D. Dettloff
,
Teva Stone
,
Kashinath Prabhu
,
Pravin Kumar Venkatesan
,
Fred Heaton
,
Ravi T. Kollipara
,
Yi Lu
,
Chris J. Madden
,
John C. Eble
,
Lei Luo
,
Nhat Nguyen
A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems.
ISSCC
(2013)
Masum Hossain
,
Kambiz Kaviani
,
Barry Daly
,
Makarand Shirasgaonkar
,
Wayne D. Dettloff
,
Teva Stone
,
Kashinath Prabhu
,
Brian Tsang
,
John C. Eble
,
Jared Zerbe
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.
CICC
(2012)
Vijay Khawshe
,
Kapil Vyas
,
Renu Rangnekar
,
Prateek Goyal
,
Vijay Krishna
,
Kashinath Prabhu
,
Pravin Kumar Venkatesan
,
Leneesh Raghavan
,
Rajkumar Palwai
,
M. Thrivikraman
,
Kunal Desai
,
Abhijit Abhyankar
A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link.
VLSI Design
(2009)