Jafar Savoj

Publication Activity (10 Years)

Years Active: 2001-2015
Publications (10 Years): 2

Top Topics

Top Venues

IEEE J. Solid State Circuits

Publications

Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. IEEE J. Solid State Circuits 50 (8) (2015)
Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. ISSCC (2015)
Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. CICC (2014)
Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang
2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS. ISSCC (2014)
Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. IEEE J. Solid State Circuits 48 (11) (2013)
Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu
F6: Mixed-signal/RF design and modeling in next-generation CMOS. ISSCC (2013)
Jafar Savoj, Chris Mangelsdorf
Session 10 overview: Analog techniques. ISSCC (2013)
Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. CICC (2012)
Jafar Savoj, Chris Mangelsdorf
Session 21 overview: Analog techniques: Analog subcommittee. ISSCC (2012)
Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. VLSIC (2012)
Jed Hurwitz, Jafar Savoj
Technologies that could change the world - You decide! ISSCC (2012)
Ali Sheikholeslami, Franz Dielacher, Miki Moyal, Jafar Savoj, John T. Stonick, Takuji Yamamoto
High-speed transceivers: Standards, challenges, and future. ISSCC (2011)
Jafar Savoj, Yiannos Manoli, Hooman Darabi, Yorgos Palaskas, Michael Moyal
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 46 (12) (2011)
Jafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications. IEEE J. Solid State Circuits 43 (5) (2008)
Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. IEEE J. Solid State Circuits 43 (4) (2008)
Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz
Time-Variant Characterization and Compensation of Wideband Circuits. CICC (2007)
Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz
A new technique for characterization of digital-to-analog converters in high-speed systems. DATE (2007)
Jafar Savoj, David Rich, Brett Forejt, Peter R. Kinget, Un-Ku Moon, Modest M. Oprysko, Behzad Razavi, Hisashi (Sam) Shichijo, Albert Z. Wang
Will continued process-node shrinks kill high-performance analog design? CICC (2005)
Albert Z. H. Wang, Sreedhar Natarajan, Jafar Savoj
Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 40 (9) (2005)
Jafar Savoj, Ramesh Harjani
Clocking circuits for wireline communications. CICC (2005)
Jafar Savoj, Behzad Razavi
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector. IEEE J. Solid State Circuits 38 (1) (2003)
Jafar Savoj, Behzad Razavi
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems. DAC (2001)
Jafar Savoj, Behzad Razavi
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. IEEE J. Solid State Circuits 36 (5) (2001)