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Ade Bekele
Publication Activity (10 Years)
Years Active: 2012-2023
Publications (10 Years): 6
Top Topics
Cmos Technology
Frequency Response
Sar Images
High Speed
Top Venues
ISSCC
VLSI Circuits
IEEE J. Solid State Circuits
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Publications
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Mayank Raj
,
Chuan Xie
,
Ade Bekele
,
Adam Chou
,
Wenfeng Zhang
,
Ying Cao
,
Jae Wook Kim
,
Nakul Narang
,
Hongyuan Zhao
,
Yipeng Wang
,
Kee Hian Tan
,
Winson Lin
,
Jay Im
,
David Mahashin
,
Santiago Asuncion
,
Parag Upadhyaya
,
Yohan Frans
A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.
ISSCC
(2023)
Jay Im
,
Kevin Zheng
,
Chuen-Huei Adam Chou
,
Lei Zhou
,
Jae Wook Kim
,
Stanley Chen
,
Yipeng Wang
,
Hao-Wei Hung
,
Kee Hian Tan
,
Winson Lin
,
Arianne Roldan
,
Declan Carey
,
Ilias Chlis
,
Ronan Casey
,
Ade Bekele
,
Ying Cao
,
David Mahashin
,
Hong Ahn
,
Hongtao Zhang
,
Yohan Frans
,
Ken Chang
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.
IEEE J. Solid State Circuits
56 (1) (2021)
Jay Im
,
Kevin Zheng
,
Adam Chou
,
Lei Zhou
,
Jae Wook Kim
,
Stanley Chen
,
Yipeng Wang
,
Hao-Wei Hung
,
Kee Hian Tan
,
Winson Lin
,
Arianne Roldan
,
Declan Carey
,
Ilias Chlis
,
Ronan Casey
,
Ade Bekele
,
Ying Cao
,
David Mahashin
,
Hong Ahn
,
Hongtao Zhang
,
Yohan Frans
,
Ken Chang
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.
ISSCC
(2020)
Didem Turker
,
Ade Bekele
,
Parag Upadhyaya
,
Bob Verbruggen
,
Ying Cao
,
Shaojun Ma
,
Christophe Erdmann
,
Brendan Farley
,
Yohan Frans
,
Ken Chang
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.
ISSCC
(2018)
Jay Im
,
Stanley Chen
,
Dave Freitas
,
Adam Chou
,
Lei Zhou
,
Ian Zhuang
,
Tim Cronin
,
David Mahashin
,
Winson Lin
,
Kok Lim Chan
,
Hongyuan Zhao
,
Kee Hian Tan
,
Ade Bekele
,
Didem Turker
,
Parag Upadhyaya
,
Yohan Frans
,
Ken Chang
A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.
VLSI Circuits
(2018)
Parag Upadhyaya
,
Ade Bekele
,
Didem Turkur Melek
,
Haibing Zhao
,
Jay Im
,
Junho Cho
,
Kee Hian Tan
,
Scott McLeod
,
Stanley Chen
,
Wenfeng Zhang
,
Yohan Frans
,
Ken Chang
A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.
VLSI Circuits
(2016)
Parag Upadhyaya
,
Jafar Savoj
,
Fu-Tai An
,
Ade Bekele
,
Anup P. Jose
,
Bruce Xu
,
Zhaoyin Daniel Wu
,
Didem Turker
,
Hesam Amir Aslanzadeh
,
Hiva Hedayati
,
Jay Im
,
Siok-Wei Lim
,
Stanley Chen
,
Toan Pham
,
Yohan Frans
,
Ken Chang
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.
ISSCC
(2015)
Jafar Savoj
,
Kenny C.-H. Hsieh
,
Parag Upadhyaya
,
Fu-Tai An
,
Ade Bekele
,
Stanley Chen
,
Xuewen Jiang
,
Kang Wei Lai
,
Chi Fung Poon
,
Aman Sewani
,
Didem Turker
,
Karthik Venna
,
Zhaoyin Daniel Wu
,
Bruce Xu
,
Elad Alon
,
Ken Chang
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.
VLSIC
(2012)