A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.
Didem TurkerAde BekeleParag UpadhyayaBob VerbruggenYing CaoShaojun MaChristophe ErdmannBrendan FarleyYohan FransKen ChangPublished in: ISSCC (2018)
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