Christophe Erdmann

Publication Activity (10 Years)

Years Active: 2014-2021
Publications (10 Years): 11

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Heterogeneous Sources

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Publications

Shantanu Mehta, Roberto Pelliconi, Christophe Erdmann, Vincent O'Brien, Brendan Mullane
Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters. IEEE Open J. Circuits Syst. 2 (2021)
Shantanu Mehta, Brendan Mullane, Vincent O'Brien, Roberto Pelliconi, Christophe Erdmann
A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters. ISCAS (2021)
Shantanu Mehta, Brendan Mullane, Vincent O'Brien, Roberto Pelliconi, Christophe Erdmann
A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC. ICECS (2020)
Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. ISSCC (2018)
Christophe Erdmann, Bob Verbruggen, Bruno Vaz, Roberto Pelliconi, John McGrath, Ryan Kinnerk, Ronnie De La Torre, John O'Dwyer, Patrick Lynch, Padraig Kelly, Peng Lim, Daire Breathnach, Brendan Farley
A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC. VLSI Circuits (2018)
Bruno Vaz, Bob Verbruggen, Christophe Erdmann, Diarmuid Collins, John McGrath, Ali Boumaalif, Edward Cullen, Darragh Walsh, Alonso Morgado, Conrado Mesadri, Brian Long, Rajitha Pathepuram, Ronnie De La Torre, Alvin Manlapat, Georgios Karyotis, Dimitris Tsaliagos, Patrick Lynch, Peng Lim, Daire Breathnach, Brendan Farley
A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET. VLSI Circuits (2018)
Brendan Farley, John McGrath, Christophe Erdmann
An All-Programmable 16-nm RFSoC for Digital-RF Communications. IEEE Micro 38 (2) (2018)
Christophe Erdmann, Edward Cullen, Damien Brouard, Roberto Pelliconi, Bob Verbruggen, John McGrath, Diarmuid Collins, Marites De La Torre, Pierrick Gay, Patrick Lynch, Peng Lim, Anthony Collins, Brendan Farley
16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz. ISSCC (2017)
Bruno Vaz, Adrian Lynam, Bob Verbruggen, Asma Laraba, Conrado Mesadri, Ali Boumaalif, John McGrath, Umanath Kamath, Ronnie De La Torre, Alvin Manlapat, Daire Breathnach, Christophe Erdmann, Brendan Farley
16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. ISSCC (2017)
Brendan Farley, Christophe Erdmann, Bruno Vaz, John McGrath, Edward Cullen, Bob Verbruggen, Roberto Pelliconi, Daire Breathnach, Peng Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, David Melinn, Kwee Peng Yap, Liam Madden
A programmable RFSoC in 16nm FinFET technology for wideband communications. A-SSCC (2017)
Christophe Erdmann, Donnacha Lowney, Adrian Lynam, Aidan Keady, John McGrath, Edward Cullen, Daire Breathnach, Denis Keane, Patrick Lynch, Marites De La Torre, Ronnie De La Torre, Peng Lim, Anthony Collins, Brendan Farley, Liam Madden
A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters. IEEE J. Solid State Circuits 50 (1) (2015)
Christophe Erdmann, Donnacha Lowney, Adrian Lynam, Aidan Keady, John McGrath, Edward Cullen, Daire Breathnach, Denis Keane, Patrick Lynch, Marites De La Torre, Ronnie De La Torre, Peng Lim, Anthony Collins, Brendan Farley, Liam Madden
6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters. ISSCC (2014)