Brendan Mullane

Publication Activity (10 Years)

Years Active: 2007-2021
Publications (10 Years): 11

Top Topics

Discriminant Function

Hardware Implementation

Top Venues

IEEE Open J. Circuits Syst.

Circuits Syst. Signal Process.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Shantanu Mehta, Roberto Pelliconi, Christophe Erdmann, Vincent O'Brien, Brendan Mullane
Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters. IEEE Open J. Circuits Syst. 2 (2021)
Fotios Kostarelos, Ciaran MacNamee, Brendan Mullane
A Hardware Implementation of a qEEG-Based Discriminant Function for Brain Injury Detection. BioCAS (2021)
Shantanu Mehta, Brendan Mullane, Vincent O'Brien, Roberto Pelliconi, Christophe Erdmann
A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters. ISCAS (2021)
Shantanu Mehta, Daniel O'Hare, Vincent O'Brien, Eric Thompson, Brendan Mullane
Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs. IEEE Open J. Circuits Syst. 1 (2020)
Shantanu Mehta, Brendan Mullane, Vincent O'Brien, Roberto Pelliconi, Christophe Erdmann
A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC. ICECS (2020)
Vincent O'Brien, Brendan Mullane
High Order Mismatch Shaping for Low Oversampling Rates. IEEE Trans. Circuits Syst. II Express Briefs (1) (2020)
Shantanu Mehta, Anthony G. Scanlan, Brendan Mullane, Daniel O'Hare
A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance. NEWCAS (2019)
Brendan Mullane, Vincent O'Brien
An In-Place Processor Design for Real-Value FFTs Targeting in-situ Dynamic ADC Test. MWSCAS (2018)
Vincent O'Brien, Anthony G. Scanlan, Brendan Mullane
A Reduced Hardware ISI and Mismatch Shaping DEM Decoder. Circuits Syst. Signal Process. 37 (6) (2018)
Daniel O'Hare, Anthony G. Scanlan, Eric Thompson, Brendan Mullane
Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Vincent O'Brien, Anthony G. Scanlan, Brendan Mullane
Correction to: A Reduced Hardware ISI and Mismatch Shaping DEM Decoder. Circuits Syst. Signal Process. 37 (6) (2018)
Christopher Bailey, Brendan Mullane
Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics. VLSI Design 2014 (2014)
Hongjia Mo, Michael Peter Kennedy, Vincent O'Brien, Brendan Mullane
Experimental validation of DAC with nested bus-splitting EFM4 DDSM. ECCTD (2013)
Brendan Mullane, Vincent O'Brien
A 100dB SFDR 0.5V pk-pk Band-Pass DAC Implemented on a Low Voltage CMOS Process. VLSI-SoC (Selected Papers) (2011)
Brendan Mullane, Vincent O'Brien
A high performance band-pass DAC architecture and design targeting a low voltage silicon process. VLSI-SoC (2011)
Vincent O'Brien, Brendan Mullane
High order mismatch noise shaping for bandpass DACs. ICECS (2011)
Michael Higgins, Ciaran MacNamee, Brendan Mullane
Design and implementation challenges for adoption of the IEEE 1500 standard. IET Comput. Digit. Tech. 4 (1) (2010)
Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann
An SOC platform for ADC test and measurement. DDECS (2009)
Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann
A prototype platform for system-on-chip ADC test and measurement. SoCC (2009)
Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann
A2DTest: A complete integrated solution for on-chip ADC self-test and analysis. ITC (2009)
Brendan Mullane, Ciaran MacNamee, Vincent O'Brien, Thomas Fleischmann
An on-chip solution for static ADC test and measurement. ACM Great Lakes Symposium on VLSI (2009)
Michael Higgins, Ciaran MacNamee, Brendan Mullane
A Novel System on Chip (SoC) Test Solution. ISVLSI (2008)
Michael Higgins, Ciaran MacNamee, Brendan Mullane
SoCECT: System on Chip Embedded Core Test. DDECS (2008)
Brendan Mullane, Michael Higgins, Ciaran MacNamee
IEEE 1500 Core Wrapper Optimization Techniques and Implementation. ITC (2008)
Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook
FPGA Prototyping of a Scan Based System-On-Chip Design. ReCoSoC (2007)