Chen-Huan Chiang

Publication Activity (10 Years)

Years Active: 1994-2011
Publications (10 Years): 0

Publications

Ujjwal Guin, Chen-Huan Chiang
Design for Bit Error Rate estimation of high speed serial links. VTS (2011)
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
A Common Language Framework for Next-Generation Embedded Testing. IEEE Des. Test Comput. 27 (5) (2010)
Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
A New Language Approach for IJTAG. ITC (2008)
Bradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker
Problems Using Boundary-Scan for Memory Cluster Tests. ITC (2008)
Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook
FPGA Prototyping of a Scan Based System-On-Chip Design. ReCoSoC (2007)
Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren
A practical approach to comprehensive system test & debug using boundary scan based test architecture. ITC (2007)
Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung
Testing and Remote Field Update of Distributed Base Stations in a Wireless Network. ITC (2004)
Tapan J. Chakraborty, Chen-Huan Chiang
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. ITC (2002)
Chen-Huan Chiang, Sandeep K. Gupta
BIST TPG for Combinational Cluster Interconnect Testing at Board Level. J. Electron. Test. 16 (5) (2000)
Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace
End-to-end testing for boards and systems using boundary scan. ITC (2000)
Chen-Huan Chiang, Sandeep K. Gupta
BIST TPG for SRAM cluster interconnect testing at board level. Asian Test Symposium (2000)
Chen-Huan Chiang, Sandeep K. Gupta
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. Asian Test Symposium (1998)
Chen-Huan Chiang, Sandeep K. Gupta
BIST TPG for faults in system backplanes. ICCAD (1997)
Chen-Huan Chiang, Sandeep K. Gupta
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. VTS (1997)
Chen-Huan Chiang, Sandeep K. Gupta
Random pattern testable logic synthesis. ICCAD (1994)