Yipeng Wang

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 8

Top Topics

Fully Integrated

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans
A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. ISSCC (2023)
Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. IEEE J. Solid State Circuits 57 (4) (2022)
Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans
A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. VLSI Circuits (2021)
Jay Im, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. IEEE J. Solid State Circuits 56 (1) (2021)
Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. ISSCC (2020)
Quan Pan, Yipeng Wang, C. Patrick Yue
A 42-dB Ω 25-Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications. IEEE Trans. Circuits Syst. II Express Briefs (1) (2020)
Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang
A 112-GB/S PAM4 Transmitter in 16NM FinFET. VLSI Circuits (2018)
Yipeng Wang, Duona Luo, Quan Pan, Liwen Jing, Zhixin Li, C. Patrick Yue
A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2017)
Yan Lu, Yipeng Wang, Quan Pan, Wing-Hung Ki, C. Patrick Yue
A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Yipeng Wang, Duona Luo, Quan Pan, Liwen Jing, Zhixin Li, C. Patrick Yue
A 60GHz 4Gb/s fully integrated NRZ-to-QPSK modulator SoC for backhaul links in fiber-wireless networks. ESSCIRC (2015)
Quan Pan, Zhengxiong Hou, Yipeng Wang, Yan Lu, Wing-Hung Ki, Keh-Chung Wang, C. Patrick Yue
A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer. VLSIC (2014)
Quan Pan, Yipeng Wang, Zhengxiong Hou, Li Sun, Liang Wu, Wing-Hung Ki, Patrick Chiang, C. Patrick Yue
A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization. ESSCIRC (2014)
Zhengxiong Hou, Yipeng Wang, Quan Pan, C. Patrick Yue
A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers. ASICON (2013)
Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Patrick Yue
A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical. ASICON (2013)