Sai Lalith Chaitanya Ambatipudi

Publication Activity (10 Years)

Years Active: 2018-2020
Publications (10 Years): 5

Top Topics

Multiresolution

Amplitude Modulation

Top Venues

IEEE J. Solid State Circuits

Publications

Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang
50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. ECOC (2020)
Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. IEEE J. Solid State Circuits 55 (4) (2020)
Mayank Raj, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang
A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. VLSI Circuits (2019)
Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang
A 112-GB/S PAM4 Transmitter in 16NM FinFET. VLSI Circuits (2018)
James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. VLSI Circuits (2018)