A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.
James HudnerDeclan CareyRonan CaseyKay HearnePedro Wilson de Abreu Farias NetoIlias ChlisMarc ErettChi Fung PoonAsma LarabaHongtao ZhangSai Lalith Chaitanya AmbatipudiDavid MahashinParag UpadhyayaYohan FransKen ChangPublished in: VLSI Circuits (2018)