Ping-Chuan Chiang

Publication Activity (10 Years)

Years Active: 2011-2020
Publications (10 Years): 9

Top Topics

Cmos Technology

Top Venues

IEEE J. Solid State Circuits

Publications

Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang
50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. ECOC (2020)
Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. IEEE J. Solid State Circuits 55 (4) (2020)
Marc Erett, Declan Carey, Ronan Casey, James Hudner, Kevin Geary, Ted Lee, Mayank Raj, Hongtao Zhang, Arianne Roldan, Hongyuan Zhao, Ping-Chuan Chiang, Haibing Zhao, Nakul Narang, Pedro Neto, Bruce Xu, Winson Lin, Kee Hian Tan, Yohan Frans, Ken Chang
A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET. CICC (2019)
Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang
A 112-GB/S PAM4 Transmitter in 16NM FinFET. VLSI Circuits (2018)
Marc Erett, Declan Carey, James Hudner, Ronan Casey, Kevin Geary, Pedro Neto, Mayank Raj, Scott McLeod, Hongtao Zhang, Arianne Roldan, Hongyuan Zhao, Ping-Chuan Chiang, Haibing Zhao, Kee Hian Tan, Yohan Frans, Ken Chang
A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET. ISSCC (2018)
Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ping-Chuan Chiang, Ken Chang
A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS. IEEE J. Solid State Circuits 52 (10) (2017)
Jri Lee, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, Chih-Chi Weng
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies. IEEE J. Solid State Circuits 50 (9) (2015)
Jri Lee, Ping-Chuan Chiang, Chih-Chi Weng
56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS. VLSIC (2015)
Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50 (2) (2015)
Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee
2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS. ISSCC (2014)
Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee
100Gb/s ethernet chipsets in 65nm CMOS technology. ISSCC (2013)
Chin-Fu Li, Chang-Ming Lai, Ping-Chuan Chiang, Po-Chiun Huang
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension. ISOCC (2011)