100Gb/s ethernet chipsets in 65nm CMOS technology.

Jhih-Yu Jiang Ping-Chuan Chiang Hao-Wei Hung Chen-Lun Lin Ty Yoon Jri Lee

Published in: ISSCC (2013)

Keyphrases

cmos technology
high speed
low power
spl times
low voltage
parallel processing
single chip
silicon on insulator
power consumption
image sensor
real time
power dissipation
mixed signal
tcp ip
digital signal processing
signal to noise ratio
multi view
digital images