Jieh-Tsorng Wu

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 10

Top Topics

Spatially Varying

Cmos Image Sensor

Analog To Digital Converter

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Ding-Hao Wang, Jieh-Tsorng Wu
A Digital Jitter Compensation Technique for Analog-to-Digital Converters. ISCAS (2023)
Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC (2023)
Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Yong Qu, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. IEEE J. Solid State Circuits 56 (8) (2021)
Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. ESSCIRC (2019)
Sheng-Hui Liao, Jieh-Tsorng Wu
A 1-V 175- $\mu$ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques. IEEE J. Solid State Circuits 54 (9) (2019)
Sheng-Hui Liao, Jieh-Tsorng Wu
A 1 V 175 μW 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques. CICC (2018)
Chih-Min Chang, Jieh-Tsorng Wu
A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2017)
Chih-Min Chang, Jieh-Tsorng Wu
A computationally-efficient PWM technique for digital class-D amplifiers. ISCAS (2016)
Makoto Takamiya, Jieh-Tsorng Wu, Jussi Ryynänen, Kenichi Okada, Jaeha Kim
Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 50 (12) (2015)
Yung-Hui Chung, Jieh-Tsorng Wu
A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Su-Hao Wu, Jieh-Tsorng Wu
A 81-dB Dynamic Range 16-MHz Bandwidth ΔΣ Modulator Using Background Calibration. IEEE J. Solid State Circuits 48 (9) (2013)
Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu
F6: Mixed-signal/RF design and modeling in next-generation CMOS. ISSCC (2013)
Su-Hao Wu, Jieh-Tsorng Wu
Background calibration of integrator leakage in discrete-time delta-sigma modulators. NEWCAS (2013)
Chia-Ling Chang, Jieh-Tsorng Wu
A 1-V 100-dB dynamic range 24.4-kHz bandwidth delta-sigma modulator. ISCAS (2013)
Bing-Nan Fang, Jieh-Tsorng Wu
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation. IEEE J. Solid State Circuits 48 (3) (2013)
Yun Chai, Jieh-Tsorng Wu
A 5.37mW 10b 200MS/s dual-path pipelined ADC. ISSCC (2012)
Yun Chai, Jieh-Tsorng Wu
A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC. IEEE J. Solid State Circuits 47 (12) (2012)
Bing-Nan Fang, Jieh-Tsorng Wu
A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps. ISCAS (2012)
Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu
A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz. ISSCC (2011)
Wei-Hsin Tseng, Jieh-Tsorng Wu, Yung-Cheng Chu
A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero. IEEE Trans. Circuits Syst. II Express Briefs (1) (2011)
Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz. IEEE J. Solid State Circuits 46 (12) (2011)
Chun-Cheng Huang, Chung-Yi Wang, Jieh-Tsorng Wu
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques. IEEE J. Solid State Circuits 46 (4) (2011)
Yung-Hui Chung, Jieh-Tsorng Wu
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC. IEEE J. Solid State Circuits 45 (11) (2010)
Chi-Wei Fan, Jieh-Tsorng Wu
ADC clock jitter measurement and correction using a stochastic TDC. APCCAS (2010)
Chung-Yi Wang, Jieh-Tsorng Wu
A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2009)
Chi-Wei Fan, Jieh-Tsorng Wu
Jitter Measurement and Compensation for Analog-to-Digital Converters. IEEE Trans. Instrum. Meas. 58 (11) (2009)
Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu
A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration. IEEE J. Solid State Circuits 42 (10) (2007)
Jen-Lin Fan, Chung-Yi Wang, Jieh-Tsorng Wu
A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2007)
Chung-Yi Wang, Jieh-Tsorng Wu
A background timing-skew calibration technique for time-interleaved analog-to-digital converters. IEEE Trans. Circuits Syst. II Express Briefs (4) (2006)
Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu
A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration. CICC (2006)
Ju-Ming Chou, Yu-Tang Hsieh, Jieh-Tsorng Wu
Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2006)
Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu
A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE J. Solid State Circuits 40 (5) (2005)
Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu
Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration". IEEE J. Solid State Circuits 40 (11) (2005)
Chun-Cheng Huang, Jieh-Tsorng Wu
A background comparator calibration technique for flash analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2005)
Jen-Lin Fan, Jieh-Tsorng Wu
A robust background calibration technique for switched-capacitor pipelined ADCs. ISCAS (2) (2005)
Chun-Cheng Huang, Jieh-Tsorng Wu
A statistical background calibration technique for flash analog-to-digital converters. ISCAS (1) (2004)
Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang
Multi-level memory systems using error control codes. ISCAS (2) (2004)
Cheng-Chung Hsu, Jieh-Tsorng Wu
A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier. IEEE J. Solid State Circuits 38 (10) (2003)
Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu
A digital background calibration technique for pipelined analog-to-digital converters. ISCAS (1) (2003)
Cheng-Chung Hsu, Jieh-Tsorng Wu
Highly linear 100 MHz CMOS programmable gain amplifiers. ISCAS (1) (2001)
Wei-Zen Chen, Jieh-Tsorng Wu
A 2-V, 1.8-GHz BJT phase-locked loop. IEEE J. Solid State Circuits 34 (6) (1999)
Wei-Zen Chen, Jieh-Tsorng Wu
A 2 V 1.6 GHz BJT phase-locked loop. CICC (1998)
Wei-Zen Chen, Jieh-Tsorng Wu
A 2-V 2-GHz BJT variable frequency oscillator. IEEE J. Solid State Circuits 33 (9) (1998)
Jieh-Tsorng Wu, Kuen-Long Chang
MOS charge pumps for low-voltage operation. IEEE J. Solid State Circuits 33 (4) (1998)