A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz.

Wei-Hsin Tseng Chi-Wei Fan Jieh-Tsorng Wu

Published in: IEEE J. Solid State Circuits (2011)

Keyphrases

nm technology
cmos technology
power consumption
low power
high speed
low voltage
random access memory
low cost
power dissipation
flip flops
database
parallel processing
max csp
mixed signal
analog to digital converter
collaborative learning