Chien-Ching Lin

Publication Activity (10 Years)

Years Active: 2003-2010
Publications (10 Years): 0

Publications

Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. IEEE J. Solid State Circuits 45 (2) (2010)
Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. Circuits Syst. II Express Briefs (9) (2009)
Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua
Multi-mode message passing switch networks applied for QC-LDPC decoder. ISCAS (2008)
Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu
Self-Compensation Technique for Simplified Belief-Propagation Algorithm. IEEE Trans. Signal Process. 55 (6-2) (2007)
Terng-Ren Hsu, Chien-Ching Lin, Terng-Yin Hsu, Chen-Yi Lee
MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2007)
Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. CICC (2007)
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
A low power turbo/Viterbi decoder for 3GPP2 applications. IEEE Trans. Very Large Scale Integr. Syst. 14 (4) (2006)
Lei-Fone Chen, Yuan Chen, Lu-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee
A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications. ISSCC (2006)
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
Design of a power-reduction Viterbi decoder for WLAN applications. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2005)
Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee
A 3.33Gb/s (1200,720) low-density parity check code decoder. ESSCIRC (2005)
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
A dual mode channel decoder for 3GPP2 mobile wireless communications. ESSCIRC (2004)
Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
A power and area efficient multi-mode FEC processor. ISCAS (2) (2004)
Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang
Multi-level memory systems using error control codes. ISCAS (2) (2004)
Chien-Ching Lin, Chia-Cho Wu, Chen-Yi Lee
A low power and high speed Viterbi decoder chip for WLAN applications. ESSCIRC (2003)