Chih-Lung Chen

Publication Activity (10 Years)

Years Active: 2008-2022
Publications (10 Years): 7

Top Topics

Decoding Algorithm

Intrusion Detection

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Commun. Lett.

Publications

Jung-San Lee, Ying-Chin Chen, Chit-Jie Chew, Chih-Lung Chen, Thu-Nguyet Huynh, Chung-Wei Kuo
CoNN-IDS: Intrusion detection system based on collaborative neural networks and agile training. Comput. Secur. 122 (2022)
Chit-Jie Chew, Ying-Chin Chen, Jung-San Lee, Chih-Lung Chen, Kuo-Yu Tsai
Preserving indomitable DDoS vitality through resurrection social hybrid botnet. Comput. Secur. 106 (2021)
Yong-Ru Lu, Shen-Iuan Liu, Yu-Che Yang, Han-Chang Kang, Chih-Lung Chen, Ka-Un Chan, Ying-Hsi Lin
A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68 (3) (2021)
Wei-Chih Hong, Ding-Ray Huang, Chih-Lung Chen, Jung-San Lee
Towards Accurate and Efficient Classification of Power System Contingencies and Cyber-Attacks Using Recurrent Neural Networks. IEEE Access 8 (2020)
Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. A-SSCC (2016)
Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. IEEE Trans. Circuits Syst. II Express Briefs (9) (2016)
Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. ISCAS (2015)
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs (3) (2015)
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC (2015)
Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. ISCAS (2014)
Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee
MLP) for big data analysis and applications. VLSIC (2014)
Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. A-SSCC (2014)
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes. WCSP (2013)
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes. IEEE Commun. Lett. 17 (5) (2013)
Hsiu-Chi Chang, Chih-Lung Chen, Hsie-Chia Chang
An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes. IEEE Commun. Lett. 17 (10) (2013)
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, John K. Zao, Hsie-Chia Chang
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection. IEEE Trans. Multim. 15 (8) (2013)
Kuo-Kuang Yen, Chih-Lung Chen, Hsie-Chia Chang
An improved LT encoding scheme with extended chain lengths. ISITA (2012)
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
Stochastic decoding for LDPC convolutional codes. ISCAS (2012)
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
Non-repetitive encoding with increased degree-1 encoding symbols for LT codes. APCCAS (2012)
Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. IEEE J. Solid State Circuits 47 (4) (2012)
Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 47 (9) (2012)
Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. IEEE J. Solid State Circuits 45 (11) (2010)
Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee
A 11.5-Gbps LDPC decoder based on CP-PEG code construction. ESSCIRC (2009)
Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. Circuits Syst. II Express Briefs (9) (2009)
Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. IEEE J. Solid State Circuits 43 (3) (2008)