Yi-Min Lin

Publication Activity (10 Years)

Years Active: 2008-2015
Publications (10 Years): 0

Top Topics

Error Correcting

Communication Systems

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee
A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang
A fully parallel BCH codec with double error correcting capability for NOR flash applications. ICASSP (2012)
Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems. ESSCIRC (2011)
Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. IEEE Trans. Circuits Syst. II Express Briefs (10) (2011)
Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. IEEE J. Solid State Circuits 45 (11) (2010)
Jao-Hong Cheng, Huei-Ping Chen, Yi-Min Lin
A hybrid forecast marketing timing model based on probabilistic neural network, rough set and C4.5. Expert Syst. Appl. 37 (3) (2010)
Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
An improved soft BCH decoder with one extra error compensation. ISCAS (2010)
Yi-Min Lin, Dong-Her Shih
Deconstructing mobile commerce service with continuance intention. Int. J. Mob. Commun. 6 (1) (2008)