A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.
Yi-Min LinChi-Heng YangChih-Hsiang HsuHsie-Chia ChangChen-Yi LeePublished in: IEEE Trans. Circuits Syst. II Express Briefs (2011)
Keyphrases
- flash memory
- parallel architecture
- embedded systems
- hand held devices
- solid state
- garbage collection
- storage devices
- file system
- parallel processing
- main memory
- random access
- hardware implementation
- systolic array
- b tree
- disk drives
- data storage
- distributed memory
- shared memory
- parallel implementation
- high level synthesis
- storage systems
- small size
- database systems
- personal computer
- low cost
- index structure
- pattern recognition