Hsie-Chia Chang

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 25

Top Venues

A-SSCC

IEEE Trans. Circuits Syst. I Regul. Pap.

ISCAS

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yu-Lun Hsu, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation. IEEE Open J. Circuits Syst. 5 (2024)
Xiao-Juan Huang, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang, Sau-Gee Chen
A MATE-GDBF Algorithm for Irregular Punctured LDPC Codes and Its Decoder Implementation. APCCAS (2023)
Li-Wei Liu, Mu-Hua Yuan, Yen-Chin Liao, Hsie-Chia Chang
A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories. IEEE Open J. Circuits Syst. 3 (2022)
Li-Wei Liu, Yen-Ching Liao, Hsie-Chia Chang
A Clustering-based ML Scheme for Capacity Approaching Soft Level Sensing in 3D TLC NAND. ICASSP (2022)
Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications. IEEE Open J. Circuits Syst. 3 (2022)
Shao Wen Cheng, Kai Jyun Hung, Hsie-Chia Chang, Yen-Chin Liao
An Attention-based Neural Network on Multiple Speaker Diarization. AICAS (2022)
SukHwan Lim, Yongpan Liu, Luca Benini, Tanay Karnik, Hsie-Chia Chang
F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors. ISSCC (2021)
Chieh-Yu Lin, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications. ISCAS (2021)
Ya-Yun Hou, Shaopeng Lai, Hung-Kun Chang, Yun-Wen Lu, Hsie-Chia Chang
A 45.4x∼221.2x latency Improvement of SRP-5 Cryptographic Engine for Smart Grid Network. A-SSCC (2021)
Yu-En Hsu, Yen-Chin Liao, Hsie-Chia Chang
A Two-Stage Path Planning Engine for Robot Navigation System. SoCC (2021)
Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang
Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification. DATE (2020)
Wei Chiang, Hsie-Chia Chang, Chen-Yi Lee
An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications. ISCAS (2020)
Tony Chan Carusone, Mingoo Seok, Hsie-Chia Chang, Meng-Fan Chang
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 55 (1) (2020)
Yun-Wen Lu, Antoon Purnal, Simon Vandenhende, Chen-Yi Lee, Ingrid Verbauwhede, Hsie-Chia Chang
A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR. VLSI-DAT (2019)
Yen-Chin Liao, Chien Lin, Hsie-Chia Chang, Shu Lin
A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Wei-Chien Kuo, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang
ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation. SoCC (2019)
Po-Hsun Chang, Chen-Yang Lin, Chia-Hsiang Sun, Yen-Chin Liao, Hsie-Chia Chang
Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A. ISCAS (2018)
Yen-Chin Liao, Hsie-Chia Chang, Shu Lin
Generalized Globally-Coupled Low-Density Parity-Check Codes. ITW (2018)
Yen-Chin Liao, Hsie-Chia Chang, Shu Lin
Scalable Globally-Coupled Low-Density Parity Check Codes. ISTC (2018)
Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. VLSI-DAT (2018)
Yu-Ming Huang, Hsie-Chia Chang, Hsiang-Pang Li
Re-Polarization Processing in Extended Polar Codes. IEICE Trans. Commun. (10) (2017)
Szu-Chi Chung, Chun-Yuan Yu, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. A-SSCC (2016)
Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. IEEE Trans. Circuits Syst. II Express Briefs (9) (2016)
Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. ISCAS (2015)
Kelvin Yi-Tse Lai, Ming-Feng Shiu, Yi-Wen Lu, Yingchieh Ho, Yu-Chi Kao, Yu-Tao Yang, Gary Wang, Keng-Ming Liu, Hsie-Chia Chang, Chen-Yi Lee
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process. A-SSCC (2015)
Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee
Pairing Accelerator Over Characteristic Three. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder. IEEE Trans. Circuits Syst. II Express Briefs (1) (2015)
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs (3) (2015)
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC (2015)
Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Kuo-Kuang Yen, Yen-Chin Liao, Hsie-Chia Chang
Design of LT code degree distribution with profiled output ripple size. SiPS (2015)
Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. ISCAS (2014)
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee
MLP) for big data analysis and applications. VLSIC (2014)
Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. A-SSCC (2014)
Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee
A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring. A-SSCC (2014)
Hsiu-Chi Chang, Hsie-Chia Chang
Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes. IEEE Trans. Commun. 62 (6) (2014)
Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee
A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Hsiu-Chi Chang, Hsie-Chia Chang
Iterative multi-step decoding for a class of multi-step majority-logic decodable cyclic codes. ISTC (2014)
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes. WCSP (2013)
Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, Hsie-Chia Chang
A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. ISSCC (2013)
Chi-Heng Yang, Yi-Hsun Chen, Hsie-Chia Chang
An area-efficient BCH codec with echelon scheduling for NAND flash applications. ICC (2013)
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes. IEEE Commun. Lett. 17 (5) (2013)
Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. 21 (11) (2013)
Hsiu-Chi Chang, Chih-Lung Chen, Hsie-Chia Chang
An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes. IEEE Commun. Lett. 17 (10) (2013)
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
Processor with side-channel attack resistance. ISSCC (2013)
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, John K. Zao, Hsie-Chia Chang
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection. IEEE Trans. Multim. 15 (8) (2013)
Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis. IEEE J. Solid State Circuits 48 (11) (2013)
Kuo-Kuang Yen, Chih-Lung Chen, Hsie-Chia Chang
An improved LT encoding scheme with extended chain lengths. ISITA (2012)
Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
Stochastic decoding for LDPC convolutional codes. ISCAS (2012)
Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
A low cost DPA-resistant 8-bit AES core based on ring oscillators. VLSI-DAT (2012)
Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee
A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance. ISCAS (2012)
Yi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang
A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. VLSI-DAT (2012)
Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang
A fully parallel BCH codec with double error correcting capability for NOR flash applications. ICASSP (2012)
Kuo-Kuang Yen, Yen-Chin Liao, Chih-Lung Chen, Hsie-Chia Chang
Non-repetitive encoding with increased degree-1 encoding symbols for LT codes. APCCAS (2012)
Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee
An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. CHES (2012)
Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. IEEE J. Solid State Circuits 47 (4) (2012)
Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 47 (9) (2012)
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine. IEEE Trans. Circuits Syst. II Express Briefs (2) (2012)
Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee
An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor. IEEE Trans. Circuits Syst. II Express Briefs (5) (2012)
Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems. ESSCIRC (2011)
Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit. ISCAS (2011)
Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee
A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. ESSCIRC (2011)
Cheng-Chi Wong, Hsie-Chia Chang
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. IEEE Trans. Circuits Syst. II Express Briefs (10) (2011)
Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. IEEE J. Solid State Circuits 45 (11) (2010)
Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. 6 (4) (2010)
Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. APCCAS (2010)
Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee
A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance. ESSCIRC (2010)
Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
An improved soft BCH decoder with one extra error compensation. ISCAS (2010)
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs (7) (2010)
Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
A multiple code-rate turbo decoder based on reciprocal dual trellis architecture. ISCAS (2010)
Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. IEEE J. Solid State Circuits 45 (2) (2010)
Cheng-Chi Wong, Hsie-Chia Chang
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System. IEEE Trans. Circuits Syst. II Express Briefs (7) (2010)
Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee
A 11.5-Gbps LDPC decoder based on CP-PEG code construction. ESSCIRC (2009)
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. ESSCIRC (2009)
Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. CICC (2009)
Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. Circuits Syst. II Express Briefs (9) (2009)
Yi Hsuan Wu, Yu Ting Liu, Hsiu-Chi Chang, Yen-Chin Liao, Hsie-Chia Chang
Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints. ICC (2008)
Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua
Multi-mode message passing switch networks applied for QC-LDPC decoder. ISCAS (2008)
Yi-Kai Lin, Chin-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang
Structured LDPCcodes with low error floor based on PEG tanner graphs. ISCAS (2008)
Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. IEEE J. Solid State Circuits 43 (3) (2008)
Yen-Chin Liao, Chien-Ching Lin, Hsie-Chia Chang, Chih-Wei Liu
Self-Compensation Technique for Simplified Belief-Propagation Algorithm. IEEE Trans. Signal Process. 55 (6-2) (2007)
Hsiu-Chi Chang, Yen-Chin Liao, Hsie-Chia Chang
Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems. SiPS (2007)
Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. CICC (2007)
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
A low power turbo/Viterbi decoder for 3GPP2 applications. IEEE Trans. Very Large Scale Integr. Syst. 14 (4) (2006)
Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu
Carry Estimation for Two's Complement Fixed-Width Multipliers. SiPS (2006)
Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang
A self-compensation fixed-width booth multiplier and its 128-point FFT applications. ISCAS (2006)
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
Design of a power-reduction Viterbi decoder for WLAN applications. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2005)
Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee
A 3.33Gb/s (1200,720) low-density parity check code decoder. ESSCIRC (2005)
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
A dual mode channel decoder for 3GPP2 mobile wireless communications. ESSCIRC (2004)
Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
A power and area efficient multi-mode FEC processor. ISCAS (2) (2004)
Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang
Multi-level memory systems using error control codes. ISCAS (2) (2004)
Hsie-Chia Chang, Chen-Yi Lee
A Low-Power Design for Reed-Solomon Decoders. J. Circuits Syst. Comput. 12 (2) (2003)
Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. IEEE J. Solid State Circuits 36 (2) (2001)

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Publication Activity (10 Years)

Top Topics

Top Venues

Hsie-Chia Chang