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A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis.
Chen-Yang Lin
Cheng-Chi Wong
Hsie-Chia Chang
Published in:
IEEE J. Solid State Circuits (2013)
Keyphrases
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low complexity
low cost
turbo codes
high density
error control
reed solomon
high speed
source code
rate allocation
vlsi architecture