Cheng-Chi Wong

Publication Activity (10 Years)

Years Active: 2007-2015
Publications (10 Years): 0

Top Topics

Fourier Transform

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

Publications

Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder. IEEE Trans. Circuits Syst. II Express Briefs (1) (2015)
Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis. IEEE J. Solid State Circuits 48 (11) (2013)
Cheng-Chi Wong, Hsie-Chia Chang
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang
A multiple code-rate turbo decoder based on reciprocal dual trellis architecture. ISCAS (2010)
Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. IEEE J. Solid State Circuits 45 (2) (2010)
Cheng-Chi Wong, Hsie-Chia Chang
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System. IEEE Trans. Circuits Syst. II Express Briefs (7) (2010)
Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. CICC (2007)