Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.
Cheng-Chi WongMing-Wei LaiChien-Ching LinHsie-Chia ChangChen-Yi LeePublished in: IEEE J. Solid State Circuits (2010)
Keyphrases
- turbo codes
- parallel architecture
- distributed video coding
- error correction
- channel coding
- parallel processing
- compressed images
- systolic array
- hardware implementation
- shared memory
- high level synthesis
- parallel implementation
- low complexity
- video codec
- distributed memory
- wireless channels
- scalable video
- synthetic aperture sonar
- transform domain
- error propagation
- rate allocation
- packet loss
- video compression
- parallel algorithm
- rate distortion
- bayesian networks