Po-Tsang Huang

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 42

Top Topics

Genome Sequencing

Ultra Low Power

Rotational Motion

Top Venues

Publications

Wei Lu, Han-Hsiang Pei, Jheng-Rong Yu, Hung-Ming Chen, Po-Tsang Huang
A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning. ISCAS (2024)
Tourangbam Harishore Singh, Po-Tsang Huang, Kung-Shuo Kao, Chih-Shiang Cheng, Kuei-Ann Wen, Lichun Wang
Energy-Efficient Sparse FFT and Compressed Transpose Memory for mmWave FMCW Radar Sensor System. IEEE Trans. Instrum. Meas. 73 (2024)
Cheng-Chen Lin, Wei Lu, Po-Tsang Huang, Hung-Ming Chen
A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block. AICAS (2024)
Po-Yang Chen, Chang-Yun Liu, Hung-Ming Chen, Po-Tsang Huang
On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC. ISQED (2023)
Hung-Ming Chen, Chu-Wen Ho, Shih-Hsien Wu, Wei Lu, Po-Tsang Huang, Hao-Ju Chang, Chien-Nan Jimmy Liu
Reshaping System Design in 3D Integration: Perspectives and Challenges. ISPD (2023)
Shao-Cheng Wen, Po-Tsang Huang
Design Exploration of An Energy-Efficient Acceleration System for CNNs on Low-Cost Resource-Constraint SoC-FPGAs. AICAS (2022)
Yun-Ru Yang, Wei Lu, Po-Tsang Huang, Hung-Ming Chen
Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks. MCSoC (2022)
Wei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang
Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. ISOCC (2022)
Sunanda Thunder, Po-Tsang Huang
Variation Aware Training of Hybrid Precision Neural Networks with 28nm HKMG FeFET Based Synaptic Core. CoRR (2022)
Yu-Hong Chang, Tourangbam Harishore Singh, Po-Tsang Huang
Cognitive Bus Coding Scheme for Inter-Chip Communications of Deep Learning Accelerator Chiplet on Low-cost Si and Glass Interposer. MCSoC (2022)
Yannick Raffel, Sunanda Thunder, Maximilian Lederer, Ricardo Olivo, Raik Hoffmann, Luca Pirro, Sven Beyer, Talha Chohan, Po-Tsang Huang, Sourav De, Thomas Kämpfe, Konrad Seidel, Johannes Heitman
Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications. ICICDT (2022)
Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, Chih-I Wu
An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. VLSI Technology and Circuits (2022)
Jui-I Kao, Wei Lu, Po-Tsang Huang, Hung-Ming Chen
Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator. ISOCC (2022)
Amit Sravan Bora, Tourangbam Harishore Singh, Po-Tsang Huang
Digi-FH-OFDM: An all-digital wideband frequency-hopped OFDM system. Phys. Commun. 52 (2022)
Tourangbam Harishore Singh, Shabirahmed Badashasab Jigalur, Po-Tsang Huang
Rotational motion-aware beam refinement for high-throughput mmWave communications. Wirel. Networks 27 (3) (2021)
Po-Tsang Huang, I-Chen Wu, Chin-Yang Lo, Wei Hwang
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks. IEEE Open J. Circuits Syst. 2 (2021)
Po-Tsang Huang, Ting-Wei Liu, Wei Lu, Yu-Hsien Lin, Wei Hwang
An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks. ISOCC (2021)
Sunanda Thunder, Parthasarathi Pal, Yeong-Her Wang, Po-Tsang Huang
Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on α-IGZO Nanosheet and Bi-Layer Resistive Memory. CoRR (2021)
Sunanda Thunder, Parthasarathi Pal, Yeong-Her Wang, Po-Tsang Huang
Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on α-IGZO Nanosheet and Bi-Layer Resistive Memory. ICICDT (2021)
Li-Hsiang Shen, Ting-Wei Chang, Kai-Ten Feng, Po-Tsang Huang
Design and Implementation for Deep Learning Based Adjustable Beamforming Training for Millimeter Wave Communication Systems. IEEE Trans. Veh. Technol. 70 (3) (2021)
Wei Lu, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang
An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (4) (2021)
Chin-Yang Lo, Po-Tsang Huang, Wei Hwang
Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. AICAS (2020)
Kai-Ten Feng, Li-Hsiang Shen, Chi-Yu Li, Po-Tsang Huang, Sau-Hsuan Wu, Li-Chun Wang, Yi-Bing Lin, Mau-Chung Frank Chang
3D On-Demand Flying Mobile Communication for Millimeter-Wave Heterogeneous Networks. IEEE Netw. 34 (5) (2020)
Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen
Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. SoCC (2020)
I-Chen Wu, Po-Tsang Huang, Chin-Yang Lo, Wei Hwang
An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network. AICAS (2019)
Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. SoCC (2019)
Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET. NOCS (2019)
Shu-Feng Cheng, Po-Tsang Huang, Li-Chun Wang, Mau-Chung Frank Chang
Built-In Self-Test/Repair Methodology for Multiband RF-Interconnected TSV 3D Integration. IEEE Des. Test 36 (6) (2019)
Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. VLSI-DAT (2018)
Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. SoCC (2018)
Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing. FPL (2018)
Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing. FCCM (2018)
Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS (2017)
Yuan Du, Wei-Han Cho, Po-Tsang Huang, Yilei Li, Chien-Heng Wong, Jieqiong Du, Yanghyo Kim, Boyu Hu, Li Du, Chun-Chen Liu, Sheau Jiung Lee, Mau-Chung Frank Chang
A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection. IEEE J. Solid State Circuits 52 (4) (2017)
Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. IEEE Trans. Biomed. Circuits Syst. 11 (5) (2017)
Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. ISCAS (2017)
Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. SoCC (2016)
Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. VLSI Circuits (2016)
Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu
The SMEM Seeding Acceleration for DNA Sequence Alignment. FCCM (2016)
Wei-Han Cho, Yilei Li, Yuan Du, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. ISSCC (2016)
Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. ISCAS (2016)
Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT (2015)
Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang
Energy-efficient gas recognition system with event-driven power control. SoCC (2015)
Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. VLSI-DAT (2015)
Wei-Han Cho, Yilei Li, Yanghyo Kim, Po-Tsang Huang, Yuan Du, Sheau Jiung Lee, Mau-Chung Frank Chang
A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface. CICC (2015)
Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. IEEE Trans. Biomed. Circuits Syst. 8 (6) (2014)
Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. A-SSCC (2014)
Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. SoCC (2014)
Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Energy-efficient configurable discrete wavelet transform for neural sensing applications. ISCAS (2014)
Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, Ho-Ming Tong
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. ISSCC (2014)
Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. VLSI-DAT (2014)
Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. BioCAS (2013)
Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong
Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC (2013)
Po-Tsang Huang, Wei Hwang
Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electr. Comput. Eng. 2012 (2012)
Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC (2012)
Po-Jen Yang, Po-Tsang Huang, Wei Hwang
Substrate noise suppression technique for power integrity of TSV 3D integration. ISCAS (2012)
Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang
A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. VLSI-DAT (2012)
Po-Tsang Huang, Yung Chang, Wei Hwang
On-demand memory sub-system for multi-core SoCs. SoCC (2011)
Po-Tsang Huang, Wei Hwang
Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2011)
Po-Tsang Huang, Wei Hwang
A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. IEEE J. Solid State Circuits 46 (2) (2011)
Hsin Rau, Chien-Hung Wu, Wei-Jung Shiang, Po-Tsang Huang
A decision support system of statistical process control for printed circuit boards manufacturing. ICMLC (2010)
Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. 6 (4) (2010)
Tien-Hung Lin, Po-Tsang Huang, Wei Hwang
Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC (2010)
Po-Tsang Huang, Wei Hwang
An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. SoCC (2009)
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang
"Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS (2008)
Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS (2008)
Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS (2008)
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC (2008)
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC (2007)
Po-Tsang Huang, Wei-Keng Chang, Wei Hwang
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS (2006)
Jen-Wei Yang, Po-Tsang Huang, Wei Hwang
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS (2006)
Po-Tsang Huang, Wei Hwang
2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS (2006)