Chien-Nan Jimmy Liu

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 22

Top Topics

Analog Circuits

Simultaneous Optimization

Reduction Method

Top Venues

Publications

Po-Chun Wang, Mark Po-Hung Lin, Chien-Nan Jimmy Liu, Hung-Ming Chen
Layout Synthesis of Analog Primitive Cells with Variational Autoencoder. SMACD (2023)
Hung-Ming Chen, Chu-Wen Ho, Shih-Hsien Wu, Wei Lu, Po-Tsang Huang, Hao-Ju Chang, Chien-Nan Jimmy Liu
Reshaping System Design in 3D Integration: Perspectives and Challenges. ISPD (2023)
Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC (2023)
Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. ASP-DAC (2022)
Shih-Han Chang, Chien-Nan Jimmy Liu, Alexandra Küster
Behavioral Level Simulation Framework to Support Error-Aware CNN Training with In-Memory Computing. SMACD (2022)
Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen
On Optimizing Capacitor Array Design for Advanced Node SAR ADC. SMACD (2022)
Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (12) (2021)
Hao-Yu Chi, Chien-Nan Jimmy Liu, Hung-Ming Chen
Wire Load Oriented Analog Routing with Matching Constraints. ACM Trans. Design Autom. Electr. Syst. 25 (6) (2020)
Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. ICCAD (2020)
Yu-Hsien Chen, Hao-Yu Chi, Ling-Yen Song, Chien-Nan Jimmy Liu, Hung-Ming Chen
A Structure-Based Methodology for Analog Layout Generation. SMACD (2019)
Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. ICCAD (2019)
Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen
Performance-preserved analog routing methodology via wire load reduction. ASP-DAC (2018)
Hsin-Ju Hsu, Wan-Chun Chen, Long-Ching Yeh, Chien-Nan Jimmy Liu
Spec-to-Layout Automation Flow for Buck Converters with Current-Mode Control in SOC Applications. SMACD (2018)
Chih-Wei Lee, Hwa-Yi Tseng, Chi-Lien Kuo, Chien-Nan Jimmy Liu, Chin Hsia
Layout placement optimization with isolation rings for high-voltage VLSI circuits. VLSI-DAT (2017)
Nguyen Cao Qui, Si-Rong He, Chien-Nan Jimmy Liu
Cluster-based delta-QMC technique for fast yield analysis. Integr. 58 (2017)
Ling-Yen Song, Chun Wang, Chien-Nan Jimmy Liu, Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
Non-regression approach for the behavioral model generator in mixed-signal system verification. VLSI-SoC (2017)
Si-Rong He, Nguyen Cao Qui, Yu-Hsuan Kuo, Chien-Nan Jimmy Liu
An Incremental Aging Analysis Method Based on Delta Circuit Simulation Technique. ATS (2017)
Nguyen Cao Qui, Si-Rong He, Chien-Nan Jimmy Liu
An Incremental Simulation Technique Based on Delta Model for Lifetime Yield Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2017)
Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He
Wave digital filter based analog circuit emulation on FPGA. ISCAS (2016)
Ying-Chi Lien, Ching-Mao Lee, Chih-Wei Li, Ban-Han Tsai, Chien-Nan Jimmy Liu
Low-noise analog synthesis platform for bio-signal acquisition system. VLSI-DAT (2015)
Hsin-Ju Chang, Yen-Lung Chen, Conan Yeh, Chien-Nan Jimmy Liu
Layout-aware analog synthesis environment with yield consideration. ISQED (2015)
Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. ASP-DAC (2015)
Hsing-Han Tseng, Shiou-Wen Wang, Jian-Yu Chen, Chien-Nan Jimmy Liu
A novel design space reduction method for efficient simulation-based optimization. ISCAS (2014)
Yen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, Chien-Nan Jimmy Liu
Simultaneous optimization for low dropout regulator and its error amplifier with process variation. VLSI-DAT (2014)
Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen
LASER: layout-aware analog synthesis environment on laker. ACM Great Lakes Symposium on VLSI (2013)
Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, Chien-Nan Jimmy Liu
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects. DATE (2013)
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs. Integr. 46 (3) (2013)
Yen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, Chien-Nan Jimmy Liu
A layout-aware automatic sizing approach for retargeting analog integrated circuits. VLSI-DAT (2013)
Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai
A fast heuristic approach for parametric yield enhancement of analog designs. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Mu-Shun Matt Lee, Wei-Ting Liao, Chien-Nan Jimmy Liu
Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (6) (2012)
Mu-Shun Matt Lee, Yi-Chu Liu, Wan-Rong Wu, Chien-Nan Jimmy Liu
Peak wake-up current estimation at gate-level with standard library information. VLSI-DAT (2012)
Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu
Reducing test point overhead with don't-cares. MWSCAS (2012)
Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu
Improving design verifiability by early RTL coverability analysis. MEMOCODE (2012)
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. J. Inf. Sci. Eng. 27 (1) (2011)
Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu
ILP-based inter-die routing for 3D ICs. ASP-DAC (2011)
Chin-Lung Chuang, Chien-Nan Jimmy Liu
Hybrid Testbench Acceleration for Reducing Communication Overhead. IEEE Des. Test Comput. 28 (2) (2011)
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. ISQED (2011)
Mu-Shun Matt Lee, Kuo-Sheng Lai, Chia-Ling Hsu, Chien-Nan Jimmy Liu
Dynamic IR drop estimation at gate level with standard library information. ISCAS (2010)
Chin-Cheng Kuo, Chien-Nan Jimmy Liu
Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2010)
Mu-Shun Matt Lee, Chien-Nan Jimmy Liu
Dynamic Supply Current Waveform Estimation with Standard Library Information. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2010)
Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu
Behavior-level yield enhancement approach for large-scaled analog circuits. DAC (2010)
Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave. IEICE Trans. Inf. Syst. (6) (2010)
Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2010)
Hsiu-Wen Li, Ren-Hong Fu, Hsin-Yu Luo, Chien-Nan Jimmy Liu
Automatic circuit adjustment technique for process sensitivity reduction and yield improvement. ISCAS (2010)
Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Trans. Electron. (7) (2009)
Chin-Cheng Kuo, Meng-Jung Lee, Chien-Nan Jimmy Liu, Ching-Ji Huang
Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2009)
Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu
Design of an All-Digital LVDS Driver. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2009)
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. DATE (2009)
Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu
A Tree-Topology Multiplexer for Multiphase Clock System. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2009)
Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level. ASP-DAC (2009)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (2) (2009)
Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu
Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System. IEICE Trans. Commun. (11) (2009)
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. J. Inf. Sci. Eng. 24 (1) (2008)
Mu-Shun Matt Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, Shih-Che Lin
Quick supply current waveform estimation at gate level using existed cell library information. ACM Great Lakes Symposium on VLSI (2008)
Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu
A Scalable Digitalized Buffer for Gigabit I/O. IEEE Trans. Circuits Syst. II Express Briefs (10) (2008)
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
Effective decap insertion in area-array SoC floorplan design. ACM Trans. Design Autom. Electr. Syst. 13 (4) (2008)
Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, Chien-Nan Jimmy Liu, Chauchin Su
Filter Approach. IEEE Trans. Circuits Syst. Video Technol. 18 (12) (2008)
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. ASP-DAC (2007)
Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou
A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23 (1) (2007)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (8) (2007)
Chin-Lung Chuang, Wei-Hsiang Cheng, Dong-Jung Lu, Chien-Nan Jimmy Liu
Hybrid Approach to Faster Functional Verification with Full Visibility. IEEE Des. Test Comput. 24 (2) (2007)
Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu
Using power gating techniques in area-array SoC floorplan design. SoCC (2007)
Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu
An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2007)
Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu
An Efficient Approach to Build Accurate Behavioral Models of PLL Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2006)
Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su
Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Trans. Electron. (11) (2006)
Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu
A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. PATMOS (2006)
Wei-Hsiang Cheng, Chin-Lung Chuang, Chien-Nan Jimmy Liu
An efficient mechanism to provide full visibility for hardware debugging. ISCAS (2006)
Chih-Hu Wang, Bore-Kuen Lee, Wei-Hang Tseng, Chung-Hsi Fu, Chauchin Su, Chien-Nan Jimmy Liu
Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter. SMC (2006)
Chin-Cheng Kuo, Chien-Nan Jimmy Liu
On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems. VLSI-SoC (2006)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. ISCAS (6) (2005)
Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. ACM Great Lakes Symposium on VLSI (2005)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC (2005)
Wen-Tsan Hsieh, Chih-Chieh Shiue, Chien-Nan Jimmy Liu
A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. ISCAS (4) (2005)
Chin-Lung Chuang, Dong-Jung Lu, Chien-Nan Jimmy Liu
A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA. Asian Test Symposium (2004)
Yuan-Bin Sha, Mu-Shun Matt Lee, Chien-Nan Jimmy Liu
On code coverage measurement for Verilog-A. HLDVT (2004)
Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou
An efficient IP-level power model for complex digital circuits. ASP-DAC (2003)
Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
A Design-for-Verification Technique for Functional Pattern Reduction. IEEE Des. Test Comput. 20 (2) (2003)
Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou
An Efficient Power Model for IP-Level Complex Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2003)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium (2002)
Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
An efficient design-for-verification technique for HDLs. ASP-DAC (2001)
Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou
Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED (2001)
Chien-Nan Jimmy Liu, Jing-Yang Jou
An Automatic Controller Extractor for HDL Descriptions at the RTL. IEEE Des. Test Comput. 17 (3) (2000)
Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, Hsing-Ming Juan
A novel approach for functional coverage measurement in HDL. ISCAS (2000)
Chien-Nan Jimmy Liu, Jing-Yang Jou
An Efficient Functional Coverage Test for HDL Descriptions at RTL. ICCD (1999)