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Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.
Tai-Ying Jiang
Chien-Nan Jimmy Liu
Jing-Yang Jou
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2009)
Keyphrases
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design methodology
cost effective
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peer to peer overlay
optimal design
high accuracy
databases
operating system
building blocks
hardware design
highly accurate
error bounds
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knowledge base
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