Jing-Yang Jou

Publication Activity (10 Years)

Years Active: 1986-2023
Publications (10 Years): 12

Top Venues

ASP-DAC

ACM Trans. Design Autom. Electr. Syst.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

DATE

Publications

Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis. VLSI-SoC (2023)
Yu-Guang Chen, Tsung-Han Hsieh, Yi-Chen Ho, Jing-Yang Jou
A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design. AICAS (2022)
Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design. DATE (2021)
Yu-Guang Chen, Hung-Yi Chiang, Chi-Wei Hsu, Tsung-Han Hsieh, Jing-Yang Jou
A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. ISOCC (2021)
Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. ASP-DAC (2021)
Yu-Guang Chen, Chi-Wei Hsu, Hung-Yi Chiang, Tsung-Han Hsieh, Jing-Yang Jou
A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks. SoCC (2021)
Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou
Chain-based pin count minimization for general-purpose digital microfluidic biochips. ASP-DAC (2016)
Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He
Wave digital filter based analog circuit emulation on FPGA. ISCAS (2016)
An-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou
Resource-aware functional ECO patch generation. DATE (2016)
Bo-Cheng Charles Lai, Hsien-Kai Kuo, Jing-Yang Jou
A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs. IEEE Trans. Computers 64 (4) (2015)
Gung-Yu Pan, Jed Yang, Jing-Yang Jou, Bo-Cheng Charles Lai
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors. ACM Trans. Embed. Comput. Syst. 14 (4) (2015)
Gung-Yu Pan, Chih-Yen Lai, Jing-Yang Jou, Bo-Cheng Charles Lai
Power-Efficient Instancy Aware DRAM Scheduling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2015)
An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. ACM Trans. Design Autom. Electr. Syst. 20 (1) (2014)
Bu-Ching Lin, Juinn-Dar Huang, Jing-Yang Jou
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2014)
Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo, Jing-Yang Jou
A read-write aware DRAM scheduling for power reduction in multi-core systems. ASP-DAC (2014)
Gung-Yu Pan, Jing-Yang Jou, Bo-Cheng Lai
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors. ACM Trans. Design Autom. Electr. Syst. 19 (4) (2014)
Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou
Reducing Contention in Shared Last-Level Cache for Throughput Processors. ACM Trans. Design Autom. Electr. Syst. 20 (1) (2014)
Bu-Ching Lin, Ming-En Shih, Juinn-Dar Huang, Jing-Yang Jou
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors. J. Inf. Sci. Eng. 30 (4) (2014)
Gung-Yu Pan, Bo-Cheng Charles Lai, Sheng-Yen Chen, Jing-Yang Jou
A learning-on-cloud power management policy for smart devices. ICCAD (2014)
Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. ASP-DAC (2013)
Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2012)
An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou
A formal method to improve SystemVerilog functional coverage. HLDVT (2012)
Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou
Thread affinity mapping for irregular data access on shared Cache GPGPU. ASP-DAC (2012)
Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC (2011)
Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen
Design-for-debug layout adjustment for FIB probing and circuit editing. ITC (2011)
Meng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou
Mixed non-rectangular block packing for non-Manhattan layout architectures. ISQED (2011)
Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou
FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26 (5) (2010)
Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou
Expandable MDC-based FFT architecture and its generator for high-performance applications. SoCC (2010)
Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou
Unleash the parallelism of 3DIC partitioning on GPGPU. SoCC (2010)
Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu
Multiple-Fault Diagnosis Using Faulty-Region Identification. VTS (2009)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (2) (2009)
Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. Very Large Scale Integr. Syst. 17 (5) (2009)
Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. ACM Trans. Design Autom. Electr. Syst. 15 (1) (2009)
Kuang-Chin Cheng, Jing-Yang Jou
Crosstalk-avoidance coding for low-power on-chip bus. ICECS (2008)
Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou
Verification of Pin-Accurate Port Connections. IEEE Des. Test Comput. 25 (5) (2008)
Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou
A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23 (1) (2007)
Cheng-Yeh Wang, Chih-Bin Kuo, Jing-Yang Jou
Hybrid Wordlength Optimization Methods of Pipelined FFT Processors. IEEE Trans. Computers 56 (8) (2007)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (8) (2007)
Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC (2007)
Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC (2006)
Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. SoCC (2006)
Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. 11 (1) (2006)
Chia-Chih Yen, Jing-Yang Jou
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging. IEEE Trans. Computers 55 (11) (2006)
Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC (2006)
Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. HLDVT (2005)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. ISCAS (6) (2005)
Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. ASP-DAC (2005)
Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
An efficient heterogeneous tree multiplexer synthesis technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (10) (2005)
Chia-Chih Yen, Jing-Yang Jou
An optimum algorithm for compacting error traces for efficient functional debugging. HLDVT (2005)
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) (2005)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC (2005)
Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. ASP-DAC (2004)
Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou
On compliance test of on-chip bus for SOC. ASP-DAC (2004)
Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Des. Test Comput. 21 (2) (2004)
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
Layout techniques for on-chip interconnect inductance reduction. ASP-DAC (2004)
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) (2004)
Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang
An efficient logic extraction algorithm using partitioning and circuit encoding. ISCAS (5) (2004)
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (5) (2004)
Chia-Chih Yen, Jing-Yang Jou
Enhancing sequential depth computation with a branch-and-bound algorithm. HLDVT (2004)
Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. ICCD (2004)
Yi-Wei Lin, Jing-Yang Jou
An efficient approach for hierarchical submodule extraction. ISCAS (5) (2004)
Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang
Verification on Port Connections. ITC (2004)
Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou
An efficient IP-level power model for complex digital circuits. ASP-DAC (2003)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
SoC design integration by using automatic interconnection rectification. ISCAS (4) (2003)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (1) (2003)
Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
A Design-for-Verification Technique for Functional Pattern Reduction. IEEE Des. Test Comput. 20 (2) (2003)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
An automatic interconnection rectification technique for SoC design integration. ASP-DAC (2003)
Che-Hua Shih, Jing-Yang Jou
An efficient approach for error diagnosis in HDL design. ISCAS (4) (2003)
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
Simultaneous floorplanning and buffer block planning. ASP-DAC (2003)
Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou
An Efficient Power Model for IP-Level Complex Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2003)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
Heng-Liang Huang, Jing-Yang Jou
Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation. J. Circuits Syst. Comput. 11 (4) (2002)
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium (2002)
Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou
A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS (2002)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (10) (2002)
Hen-Ming Lin, Jing-Yang Jou
On tri-state buffer inference in HDL synthesis. ISCAS (5) (2001)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. Asian Test Symposium (2001)
Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou
An efficient design-for-verification technique for HDLs. ASP-DAC (2001)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
An AVPG for SOC design verification with port order fault model. ISCAS (5) (2001)
Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen
Grouped input power sensitive transition an input sequence compaction technique for power estimation. ISCAS (5) (2001)
Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou
Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED (2001)
Li-An Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu, Tai-Sheng Feng
On placement and routing of wafer scale memory. ICECS (2001)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. HLDVT (2001)
Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou
Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (1) (2001)
Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
Collaboration between Industry and Academia in Test Research. Asian Test Symposium (2000)
Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
A new method for constructing IP level power model based on power sensitivity. ASP-DAC (2000)
Chien-Nan Jimmy Liu, Jing-Yang Jou
An Automatic Controller Extractor for HDL Descriptions at the RTL. IEEE Des. Test Comput. 17 (3) (2000)
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (9) (2000)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 8 (4) (2000)
Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, Hsing-Ming Juan
A novel approach for functional coverage measurement in HDL. ISCAS (2000)
Hen-Ming Lin, Jing-Yang Jou
On computing the minimum feedback vertex set of a directed graph bycontraction operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (3) (2000)
Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
Optimal reliable crosstalk-driven interconnect optimization. ISPD (2000)
Jyh-Mou Tseng, Jing-Yang Jou
Two-level logic minimization for low power. ACM Trans. Design Autom. Electr. Syst. 4 (1) (1999)
Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC (1999)
Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang
Hierarchical Floorplan Design on the Internet. ASP-DAC (1999)
Hen-Ming Lin, Jing-Yang Jou
Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. ICCD (1999)
Chien-Nan Jimmy Liu, Jing-Yang Jou
An Efficient Functional Coverage Test for HDL Descriptions at RTL. ICCD (1999)
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
A structure-oriented power modeling technique for macrocells. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jing-Yang Jou