Wen-Zen Shen

Publication Activity (10 Years)

Years Active: 1990-2001
Publications (10 Years): 0

Publications

Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen
Grouped input power sensitive transition an input sequence compaction technique for power estimation. ISCAS (5) (2001)
Chih-Yang Hsu, Chaur-Wen Wei, Wen-Zen Shen
A pattern compaction technique for power estimation based on power sensitivity information. ISCAS (5) (2001)
Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
A new method for constructing IP level power model based on power sensitivity. ASP-DAC (2000)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 8 (4) (2000)
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
A structure-oriented power modeling technique for macrocells. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu
CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits. ASP-DAC (1997)
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
A power modeling and characterization method for macrocells using structure information. ICCAD (1997)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD (1996)
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
A power modeling and characterization method for the CMOS standard cell library. ICCAD (1996)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD (1995)
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen
Fanout fault analysis for digital logic circuits. Asian Test Symposium (1995)
Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. DAC (1995)
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
Transistor reordering rules for power reduction in CMOS gates. ASP-DAC (1995)
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
A cell-based power estimation in CMOS combinational circuits. ICCAD (1994)
Wen-Zen Shen, Yi-Hsin Tao, Lan-Rong Dung
On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design. ISCAS (1994)
Gwo-Haur Hwang, Wen-Zen Shen
Restructuring and logic minimization for testable PLA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (4) (1993)
Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan
Design of Pseudoexhaustive Testable PLA with Low Overhead. IEEE Trans. Computers 42 (7) (1993)
Wen-Jun Hsu, Wen-Zen Shen
Coalgebraic Division for Multilevel Logic Synthesis. DAC (1992)
Chung-Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang
MT-SIM a mixed-level transition fault simulator based on parallel patterns. J. Electron. Test. 3 (1) (1992)
Ching Ping Wu, Chung-Len Lee, Wen-Zen Shen
SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence. EURO-DAC (1992)
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (12) (1991)
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
Checkpoints in irredundant two-level combinational circuits. J. Electron. Test. 2 (4) (1991)
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
Single-fault fault collapsing analysis in sequential logic circuits. ITC (1990)
Tyh-Song Hwang, Chung-Len Lee, Wen-Zen Shen, Ching Ping Wu
A Parallel Pattern Mixed-Level Fault Simulator. DAC (1990)