Juinn-Dar Huang

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 37

Top Topics

Cost Minimization

Vlsi Implementation

Multiagent Evolutionary Algorithm

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Yi-Zeng Fang, Lung-Hao Lee, Juinn-Dar Huang
NYCU-NLP at EXIST 2024: Leveraging Transformers with Diverse Annotations for Sexism Identification in Social Networks. CLEF (Working Notes) (2024)
Yu-Da Chu, Pei-Hsuan Kuo, Lyu-Ming Ho, Juinn-Dar Huang
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems. AICAS (2024)
Moi Hoon Yap, Bill Cassidy, Michal Byra, Ting-Yu Liao, Huahui Yi, Adrian Galdran, Yung-Han Chen, Raphael Brüngel, Sven Koitka, Christoph M. Friedrich, Yu-Wen Lo, Ching-Hui Yang, Kang Li, Qicheng Lao, Miguel Ángel González Ballester, Gustavo Carneiro, Yi-Jen Ju, Juinn-Dar Huang, Joseph M. Pappachan, Neil D. Reeves, Vishnu Chandrabalan, Darren Dancey, Connah Kendrick
Diabetic foot ulcers segmentation challenge report: Benchmark and analysis. Medical Image Anal. 94 (2024)
Meng-Hsun Hsieh, Xuan-Hong Li, Yu-Hsiang Huang, Pei-Hsuan Kuo, Juinn-Dar Huang
A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications. ISCAS (2024)
Pei-Hsuan Kuo, Yu-Hsiang Huang, Juinn-Dar Huang
Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning. AICAS (2023)
Yu-Hsiang Huang, Pei-Hsuan Kuo, Juinn-Dar Huang
Hardware-Friendly Activation Function Designs and Its Efficient VLSI Implementations for Transformer-Based Applications. AICAS (2023)
Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis. VLSI-SoC (2023)
Ling-Yen Song, Chih-Yun Chou, Tung-Chieh Kuo, Chien-Nan Liu, Juinn-Dar Huang
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
Wei-Cheng Chou, Cheng-Wei Huang, Juinn-Dar Huang
Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets. VLSI-DAT (2022)
Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. ASP-DAC (2022)
Chia-Heng Hu, I-Hao Tseng, Pei-Hsuan Kuo, Juinn-Dar Huang
An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability. AICAS (2022)
Kang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu, Juinn-Dar Huang
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. VLSI-DAT (2022)
Yung-Han Chen, Yi-Jen Ju, Juinn-Dar Huang
Capture the Devil in the Details via Partition-then-Ensemble on Higher Resolution Images. DFUC@MICCAI (2022)
Wei-Chen Lin, Ya-Chu Chang, Juinn-Dar Huang
An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing. AICAS (2021)
Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, Chun-Yao Wang
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. ACM J. Emerg. Technol. Comput. Syst. 17 (2) (2021)
Cheng-Wei Huang, Tim-Wei Chen, Juinn-Dar Huang
All-You-Can-Fit 8-Bit Flexible Floating-Point Format for Accurate and Memory-Efficient Inference of Deep Neural Networks. CoRR (2021)
Shuaijie Ying, Sudip Roy, Juinn-Dar Huang, Shigeru Yamashita
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip. DSD (2021)
Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu, Juinn-Dar Huang
Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips. VLSI-DAT (2021)
Yi Lu, Yi-Lin Wu, Juinn-Dar Huang
A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization. AICAS (2020)
Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya
Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Yi-Lin Wu, Yi Lu, Juinn-Dar Huang
High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme. ISCAS (2020)
Ling-Yen Song, Yi-Ling Chen, Yung-Chun Lei, Juinn-Dar Huang
Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs. ICCD (2019)
Ling-Yen Song, Yu-Ying Li, Yung-Chun Lei, Juinn-Dar Huang
Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips. ISVLSI (2019)
Ankur Gupta, Juinn-Dar Huang, Shigeru Yamashita, Sudip Roy
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Kang-Yi Fan, Shigeru Yamashita, Juinn-Dar Huang
Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models. VLSI-DAT (2019)
Chun-Yu Lin, Juinn-Dar Huang, Hailong Yao, Tsung-Yi Ho
A Comprehensive Security System for Digital Microfluidic Biochips. ITC-Asia (2018)
Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. ISVLSI (2018)
Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya
Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip. DATE (2018)
Juinn-Dar Huang, Chia-Hung Liu, Wei-Hao Yang
Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips. VLSI-SoC (2018)
Yung-Chun Lei, Tien-Kuo Lin, Juinn-Dar Huang
Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips. ISVLSI (2018)
Sukanta Bhattacharjee, Yi-Ling Chen, Juinn-Dar Huang, Bhargab B. Bhattacharya
Concentration-Resilient Mixture Preparation with Digital Microfluidic Lab-on-Chip. ACM Trans. Embed. Comput. Syst. 17 (2) (2018)
Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu
Defect-aware synthesis for reconfigurable single-electron transistor arrays. VLSI-SoC (2017)
Sukanta Bhattacharjee, Sudip Poddar, Sudip Roy, Juinn-Dar Huang, Bhargab B. Bhattacharya
Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (4) (2017)
Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou
Chain-based pin count minimization for general-purpose digital microfluidic biochips. ASP-DAC (2016)
Yung-Chun Lei, Yi-Ling Chen, Juinn-Dar Huang
Reactant cost minimization through target concentration selection on microfluidic biochips. BioCAS (2016)
Yung-Chun Lei, Tung-Hsuan Lin, Juinn-Dar Huang
Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing models. SoCC (2016)
Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints. ACM J. Emerg. Technol. Comput. Syst. 12 (4) (2016)
Chi-Mei Huang, Chia-Hung Liu, Juinn-Dar Huang
Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers. DATE (2015)
Ya-Shih Huang, Han-Yuan Chang, Juinn-Dar Huang
TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2015)
Chia-Hung Liu, Kuo-Cheng Shen, Juinn-Dar Huang
Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang
Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (9) (2015)
Yi-Hang Chen, Yang Chen, Juinn-Dar Huang
ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays. VLSI-DAT (2015)
Bu-Ching Lin, Juinn-Dar Huang, Jing-Yang Jou
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2014)
Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints. DATE (2014)
Juinn-Dar Huang, Chia-Hung Liu
Sample preparation for droplet-based microfluidics. ISIC (2014)
Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang
Two-staged parallel layer-aware partitioning for 3D designs. VLSI-DAT (2014)
Bu-Ching Lin, Ming-En Shih, Juinn-Dar Huang, Jing-Yang Jou
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors. J. Inf. Sci. Eng. 30 (4) (2014)
Chia-Hung Liu, Kuang-Cheng Liu, Juinn-Dar Huang
Latency-optimization synthesis with module selection for digital microfluidic biochips. SoCC (2013)
Juinn-Dar Huang, Chia-Hung Liu, Huei-Shan Lin
Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (10) (2013)
Ting-Wei Chiang, Chia-Hung Liu, Juinn-Dar Huang
Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips. VLSI-DAT (2013)
Tsung-Yi Ho, Juinn-Dar Huang, Paul Pop
Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration. SoCC (2013)
Chia-Hung Liu, Hao-Han Chang, Tung-Che Liang, Juinn-Dar Huang
Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing. ICCAD (2013)
Juinn-Dar Huang, Chia-Hung Liu, Ting-Wei Chiang
Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees. ICCAD (2012)
Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2012)
Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang
Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only). FPGA (2012)
Chia-I Chen, Juinn-Dar Huang
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family. ISVLSI (2011)
Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC (2011)
Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang
Layer-Aware Design Partitioning for Vertical Interconnect Minimization. ISVLSI (2011)
Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho
Throughput optimization for latency-insensitive system with minimal queue insertion. ASP-DAC (2011)
Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang
Architectural exploration of 3D FPGAs towards a better balance between area and delay. DATE (2011)
Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2011)
Chia-I Chen, Juinn-Dar Huang
A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2010)
Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou
FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26 (5) (2010)
Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou
Expandable MDC-based FFT architecture and its generator for high-performance applications. SoCC (2010)
Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. ASP-DAC (2009)
Yu-Ru Hong, Juinn-Dar Huang
Reducing fault dictionary size for million-gate large circuits. ACM Trans. Design Autom. Electr. Syst. 14 (2) (2009)
Chia-I Chen, Juinn-Dar Huang
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. ASP-DAC (2009)
Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. Very Large Scale Integr. Syst. 17 (5) (2009)
Ya-Shih Huang, Yu-Ju Hong, Juinn-Dar Huang
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Nan-Shing Li, Juinn-Dar Huang, Han-Jung Huang
Low power multiplexer tree design using dynamic propagation path control. APCCAS (2008)
Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. ASP-DAC (2008)
Chih-Hui Ting, Juinn-Dar Huang, Yu-Hsiang Kao
Cycle-time-aware sequential way-access set-associative cache for low energy consumption. APCCAS (2008)
Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou
Verification of Pin-Accurate Port Connections. IEEE Des. Test Comput. 25 (5) (2008)
Yu-Ru Hong, Juinn-Dar Huang
Fault Dictionary Size Reduction for Million-Gate Large Circuits. ASP-DAC (2007)
Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC (2007)
Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC (2006)
Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC (2006)
Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. HLDVT (2005)
Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang
Verification on Port Connections. ITC (2004)
Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 8 (4) (2000)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC (1998)
Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. ASP-DAC (1997)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD (1996)
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD (1995)
Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. DAC (1995)