An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing.
Wei-Chen LinYa-Chu ChangJuinn-Dar HuangPublished in: AICAS (2021)
Keyphrases
- low power
- vlsi architecture
- power consumption
- high speed
- low cost
- cmos technology
- mixed signal
- single chip
- low power consumption
- multilayer perceptron
- high power
- real time
- logic circuits
- neural network
- nm technology
- vlsi circuits
- digital signal processing
- wireless transmission
- artificial neural networks
- multi layer perceptron
- cmos image sensor
- gate array
- signal processor