Chia-Cheng Wu

Publication Activity (10 Years)

Years Active: 2013-2021
Publications (10 Years): 13

Top Topics

Monitoring System

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, Chun-Yao Wang
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. ACM J. Emerg. Technol. Comput. Syst. 17 (2) (2021)
Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, Shigeru Yamashita
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (12) (2019)
De-Xuan Ji, Hsiao-Yu Chiang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang
A Glitch Key-Gate for Logic Locking. SoCC (2019)
Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang
Using range-equivalent circuits for facilitating bounded sequential equivalence checking. VLSI-DAT (2018)
Chia-Cheng Wu, Tung-Yuan Lee, Yung-An Lai, Hsin-Pei Wang, De-Xuan Ji, Yan-Ping Chang, Teng-Chia Wang, Chin-Heng Liu, Chun-Yao Wang, Yung-Chih Chen
A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification. ACM Great Lakes Symposium on VLSI (2018)
Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. ISVLSI (2018)
Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Yung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang
Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. DATE (2018)
Tung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang
Logic optimization with considering boolean relations. DATE (2018)
Chun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, Chia-Cheng Wu
Majority logic circuits optimisation by node merging. ASP-DAC (2017)
Chia-Cheng Wu, Li-An Wu, Yih-Fan Chen, Lu-Ting Chou
Detection of tetracycline using isothermal amplification. NEMS (2017)
Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Shie-Yuan Wang, Chia-Cheng Wu, Chih-Liang Chou
Hybridtrace: A traceroute tool for hybrid networks composed of SDN and legacy switches. ISCC (2016)
Shie-Yuan Wang, Chia-Cheng Wu, Chih-Liang Chou
Constructing an optimal spanning tree over a hybrid network with SDN and legacy switches. ISCC (2015)
Chao-Tung Yang, Jung-Chun Liu, Yun-Ting Wang, Chia-Cheng Wu, Fang-Yie Leu
An Environmental Monitoring System for Air Quality Control. ICS (2014)
Chao-Tung Yang, Jung-Chun Liu, Yun-Ting Wang, Chia-Cheng Wu, Fang-Yie Leu
Implementation of an environmental quality and harmful gases monitoring system. SMARTCOMP (2014)
Chao-Tung Yang, Jung-Chun Liu, Chi-Jui Liao, Chia-Cheng Wu, Fang-Yie Leu
On Construction of an Intelligent Environmental Monitoring System for Healthcare. PDCAT (2013)