Ching-Yi Huang

Publication Activity (10 Years)

Years Active: 2011-2020
Publications (10 Years): 10

Top Topics

Pattern Generation

Genetic Algorithm

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Chih-Jen Hsu, Chi-An Wu, Ching-Yi Huang, Kei-Yong Khoo
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk. ICCAD (2020)
Ching-Yi Huang, Chi-An (Rocky) Wu, Tung-Yuan Lee, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space. ICCAD (2019)
Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang
Using range-equivalent circuits for facilitating bounded sequential equivalence checking. VLSI-DAT (2018)
Ching-Yi Huang, Chih-Jen Hsu, Chi-An Wu, Kei-Yong Khoo
ICCAD-2017 CAD contest in resource-aware patch generation. ICCAD (2017)
Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm. J. Multiple Valued Log. Soft Comput. 27 (1) (2016)
Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Chiou-Ting Hsu
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks. IEEE Trans. Multi Scale Comput. Syst. 2 (4) (2016)
Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta, Vijaykrishnan Narayanan
Area-Aware Decomposition for Single-Electron Transistor Arrays. ACM Trans. Design Autom. Electr. Syst. 21 (4) (2016)
Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang
MajorSat: A SAT solver to majority logic. ASP-DAC (2016)
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan
Synthesis for Width Minimization in the Single-Electron Transistor Array. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang
Using structural relations for checking combinationality of cyclic circuits. DATE (2015)
Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. ASP-DAC (2015)
Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (4) (2015)
Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang
Synthesis and verification of cyclic combinational circuits. SoCC (2015)
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
Width minimization in the Single-Electron Transistor array synthesis. DATE (2014)
Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang
Rewiring for threshold logic circuit minimization. DATE (2014)
Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (10) (2013)
Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
Sensitization criterion for threshold logic circuits and its application. ICCAD (2013)
Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
On reconfigurable single-electron transistor arrays synthesis using reordering techniques. DATE (2013)
Yen-Chi Yang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen
Pattern generation for Mutation Analysis using Genetic Algorithms. ISCAS (2013)
Ching-Yi Huang, Chi-Wen Huang, Chia-Jung Wu, Gwo-Dong Chen, Kuang-Hung Chiang
Using "Learning Video Portfolio" to Enhance Students' Metacognition in Authentic Learning. ICALT (2012)
Ching-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, Chun-Yao Wang
Error Injection & Correction: An efficient formal logic restructuring algorithm. ISOCC (2012)
Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen
A probabilistic analysis method for functional qualification under Mutation Analysis. DATE (2012)
Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin
A register-transfer level testability analyzer. SoCC (2011)
Pin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang
On rewiring and simplification for canonicity in threshold logic circuits. ICCAD (2011)