Chi-An Wu

Publication Activity (10 Years)

Years Active: 2007-2021
Publications (10 Years): 3

Top Topics

Generation Algorithm

Benchmark Suite

Computation Tree Logic

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Yen-Chun Fang, Shao-Lun Huang, Chi-An Wu, Chung-Han Chou, Chih-Jen Hsu, WoeiTzy Jong, Kei-Yong Khoo
2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper. ICCAD (2021)
Chih-Jen Hsu, Chi-An Wu, Ching-Yi Huang, Kei-Yong Khoo
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk. ICCAD (2020)
Ching-Yi Huang, Chih-Jen Hsu, Chi-An Wu, Kei-Yong Khoo
ICCAD-2017 CAD contest in resource-aware patch generation. ICCAD (2017)
Chih-Jen Hsu, Chi-An Wu, Wei-Hsun Lin, Kei-Yong Khoo
ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite. ICCAD (2015)
Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Chih-Jen Hsu, Wei-Hsun Lin, Chi-An Wu, Kei-Yong Khoo
ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite. ICCAD (2014)
Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang
A counterexample-guided interpolant generation algorithm for SAT-based model checking. DAC (2013)
Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. DATE (2011)
Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang
A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. ASP-DAC (2011)
Kai-Fu Tang, Chi-An Wu, Po-Kai Huang, Chung-Yang (Ric) Huang
Interpolation-based incremental ECO synthesis for multi-error logic rectification. DAC (2011)
Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. ASP-DAC (2009)
Chih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang
Interpolant generation without constructing resolution graph. ICCAD (2009)
Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang
QuteSAT: a robust circuit-based SAT solver for complex circuit structure. DATE (2007)