A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking.
Cheng-Yin WuChi-An WuChien-Yu LaiChung-Yang (Ric) HuangPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
Keyphrases
- model checking
- generation algorithm
- bounded model checking
- formal verification
- temporal logic
- model checker
- planning domains
- automated verification
- formal specification
- finite state
- computation tree logic
- symbolic model checking
- verification method
- temporal properties
- partial order reduction
- timed automata
- asynchronous circuits
- epistemic logic
- reachability analysis
- linear temporal logic
- pspace complete
- formal methods
- transition systems
- satisfiability problem
- concurrent systems
- ai planning
- answer set programming